대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference) (Proceedings of the IEEK Conference)
대한전자공학회 (The Institute of Electronics and Information Engineers)
- 기타
- 대한전자공학회 2000년도 추계종합학술대회 논문집(4)
- 대한전자공학회 2000년도 추계종합학술대회 논문집(3)
- 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
- 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
- 대한전자공학회 2000년도 제13회 신호처리 합동 학술대회 논문집
- 대한전자공학회 2000년도 ITC-CSCC -2
- 대한전자공학회 2000년도 ITC-CSCC -1
- 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
- 대한전자공학회 2000년도 하계종합학술대회 논문집(4)
- 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
- 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
- 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
대한전자공학회 1998년도 추계종합학술대회 논문집
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This paper considers the analysis of QoS(Quality of Service) routing mechanisms to support the NGIs(Next Generation Internets). NGIs are constructing high-speed IP layer networks to support all data services. To support real time multimedia services on NGIs, it is important to satisfy the required QoS parameters on networks. To support QoS requirements for NGI networks, new QoS routing methods are essential. In this paper, serveral new QoS routing algorithms are explained. Some problems for the high speed QoS routing will be explained and possible solutions are suggested.
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In implementing real time video on demand(VOD), the increase of user on internet causes a network traffic congestion. In this paper, we programmed a CGI able to login in VOD home for limiting the number of user in solving the problem, and also applied and adaptive multimedia synchronization technique for controlling video and audio data in a network. In addition, a real time multimedia player was designed and implemented in a personal computer operating at Window95/98/NT.
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Recently, the users of internet are increasing yearly with the rapid spread of internet. So, the shortage of IPv4 address is important issue to ISP. Many ISP is searching for efficient method to use IP address in ATM Network. Korea Telecom has constructed ATM Network test-bed to verify available technologies necessary for ATM Network. This paper, concerning with the configuration of subscribers in ATM Network test bed, analyze the available usage of IP address.
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Most existing FRADs support only permanent virtual circuit-based frame relay services. But several applications such as intranets, desktop video conferencing, remote access and voice applications typically do not require the dedicated bandwidth capabilities of PVCs because connections are only occasionally needed. So it drives the need of switched virtual circuit-based FRADs which offer potentail cost savings associated with dynamic bandwidth on demand connectivity. In this paper, we describe Frame Relay Network Access System(FNAS) that provides switched virtual circuit-based frame relay access for dial-up Internet services. The hardware configuration, software architecture and call processing flow of FNAS is explained.
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IP multicasting efficiently delivers a single datagram to multiple hosts. Its benefits have been demonstrated over the past six years on MBONE. Now, as the number of subnets in the MBONE are increased, the MBONE can no longer be managed as a single, flat routing domain. Its routing scalability must be improved. In this paper, to solve problem of routing scalability, serveral new multicast models for the internet are explained.
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본 논문에서의 기존의 2선식 댁내 망을 이용하여 ISDN PRI(2.048MHz)급의 전송을 위해 DS-CDMA방식을 적용하는 방법을 제안한다. TE 와 NT 의 신호의 검출을 위해 자기의 확산코드와 정합된 단일 사용자 검출기를 사용할 수 있으나, 검출하려는 신호와 다른 사용자 신호간의 다원접속간섭(Multiple Access Interference)에 의해 시스템의 성능이 저하된다. 본 논문에서는 다원접속간섭을 효과적으로 제거할 수 있는 최소평균제곱오차 (Minimum Mean Squared Error) 다중사용자 간섭제거기를 사용하고 컴퓨터 모의실험을 통하여 성능을 분석한다.
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CDMA base station SAW filter has been designed and fabricated successfully. Through the computer simulation, SAW filter is designed to have center frequency of 69.99MHz, ripples lower than 0.7dB and rejection level lower than 50dB. To obtain low noise band pass SAW filter, Input electrode has a apodization type and output electrode has a withdrawal type. For the fabrication of the SAW filter, Al thin film is deposited to the quartz substrates. The fabricated SAW filter has center frequency of 70.5MHz, ripples of 1dB and rejection level of 45dB.
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In this paper we fabricated QMSAs for 850MHz band on the teflon substrate with
$\varepsilon_1-2.6, $ $t=1.6mm(\pm0.08)(CGP-500).$ We measured the resonant frequency and the return loss with cutting the gap region between radiation patch and ground plate by a 5mm length step by step. As a result we found that the measured data was not so bad unlike other papers when the gap region was closer to zero, especially under 10mm. -
In this paper is design of signal discriminatior system for the third generation mobile telecommunication system (IMT-2000 : International mobile telecommunication service-2000) This system is basically using multiplexing method of CDMA, TDMA and FDMA that this system can be solved third generation systems problems-Frequency bandwidth, international roaming and development new architecture of mobile telecommunication systems. Designed signal discriminator system is perfectly separated three styles multiplexing method signals that more easily, nearly and economically implementation of third generation telecommunication systems. As we develop signal discriminator we will contribute to technical evolution of mobile telecommunication for third generation and stay ahead in the interior technical accumulation in addition to international intercourse as to mobile telecommunication.
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The performance of a receiver that empolys a multi-stage inter-ference cancellation scheme for uplink fading channel is analyzed when there is carrier frequency offset. And the conditions to permit the performance improvement are analytically obtained. Numerical results show the effectiveness of the proposed system under Rayleigh fading channel assuming that carrier frequency offset is present.
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In recent years, it is required that computing support mobile user with computer. The advantage of mobile computing is that users may access all their applications from any location, whether they are in another building or a different state. So, Internet combines with mobile computing technology to make new communication environment for supporting mobility. The research for solving the problem of mobility is actively in progress. This paper describes the implementation of tunneling method for flexible bypass between specific region. Tunneling method provide mobile service to mobile hosts. IP datagram's address tranform method is IP-within-IP encapsulation by which an IP datagram may be encapsulated within an IP datagram. The developed IP-within-IP protocol can provide not only enhanced performance because it is implemented in kernel mode, but also convenience of usage to the application developers because it gives user interface as a dynamic link library. Verification of IP packet tunneling was text file transfer program.
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In this paper, we describe the design of the ATM Mux/Demux circuit between BSC and MSC for IMT-2000 Network. This ATM Mux/Demux circuit culd support 155Mbps optic interface with MSC. Using the CAM and DPRAM, this circuit performs ATM cell Mux/Demux functions in the BSC. MPC 860SAR processor was used for the signaling with MSC in this design.
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In this paper, we describe the design of the ATM adapter circuit in the BSC for IMT-2000 Network. This ATM adapter circuit can convert received ATM cell into TDM data in the BSC and vice versa. In the ATM adapter, we implemented both AAL1 and AAL5 functions to provide constant bit rate voice data and variable bit rate packet data servives, simultaneously.
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Satellite communication systems will play an important role in establishing high-speed information communication network ddue to the characteristics of flexibility of bandwidth, mobile communication, wide coverage, multipoint and broadcasting. Also satellite systems have the capability to supply terrestrial B-ISDN with flexible links for accessing networks as well as trunking networks. Therefore, satellites must provide compatibility to earth-based B-ISDN signalling interface, services and network capability. This paper proposed interworking model between terrestrial B-ISDN and satellite B-ISDN signalling protocol and illustrated basic call-process procedure of satellite B-ISDN signalling protocol supporting point-to-point and point-to-multipoint connection.
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MC-CDMA(Multi-Carrier Code Division Multiple Access) 시스템에서 전송 신호의 피크 전력 대 평균 전력(Peak-to-Average Power: PAP)율을 낮추는 방안을 제시한다. 확산 코드에 의해 결정된 각 부 캐리어의 위상 오프셋은 전송 신호의 복소 포락선 형성에 영향을 주게 되어 전송 신호의 PAP 율을 결정하게 된다. 따라서 각 부 캐리어의 위상 오프셋을 적절히 조정함으로써 PAP율을 낮출수 있다. 본 논문에서는 PAP 율을 감소시키는 부 캐리어 위상 오프셋 코드의 한 예를 제시하며, 모의 실험을 통하여 전송신호의 크기 분포 특성과 PAP 율의 감소를 확인한다.
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In this paper, an interference analyzer for communication and/or broadcasting services is developed and presented based on Monte Carlo technique, which is now under study in the International Telecommunication Union(ITU). Monte Carlo technology is a statistical approach which functions by considering many trials. For each simulation trial, a scenario is built up using a number of different random variables, such as signal and interference strengths, transmitting and receiving antenna heights, antenna gains, etc.. Furthermore, this paper shows and application example of the analyzer to examine interference influence of the PCS(IS-95) base stations affecting to the IMT-2000 FDD base station, depending on serveral service environments like rural, suburban, and urban areas. The wave propagation model used in this simulation is the modified Hata model, which is known to the suitable to Korean environments.
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In this paper, an interface method for MMS on ATM networks is proposed. It can apply to the realtime communication and the remote control in wide-area manufacturing complex and virtual factory. It is used for the downloading program, the reporting and gathering of data and the remote control for the remote client. The developed interface rule is basd on the rule for MMS on TCP/IP. The main goals of implementation are to verify whether MMS on ATM is able to meet the requirements of factory automation and manufacturing complex.
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In this paper, we propose a new cell discarding and scheduling scheme which reduce cell loss rate by measuring, in real time, the number of discarded cells in the queuing system with a different loss priority for each class of service such that each class of service meets its cell loss rate requirements and reduce average delay rate for the traffic that is sensitive in cell delay in output buffer of the ATM switch. Throughout the computer simulation, the existing scheduling scheme and proposed scheme are compared with respect to cell loss rate and average delay time.
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This paper proposes the MAC scheme based on variable reservation slots for the guaranteed QoS of ATM services on RF and evaluates the performance. This scheme has improved the utilization of channel and success ratio of reservation by using the variable number of RES(REServation) slots according to the collisions. It is the results of performance evaluation that the CTD of CBR Service is 7.9ms with overall
$load(\rho)$ 85%. And also VBR service of it is 3.5ms, ABR service of it is 9.8ms with overall load 85%. -
In recent years, security has been more and more significant in network environment. The internetworkding communication including ATM network will be exposed to all kinds of attacks, such as eavesdropping, spoofing, service denial and traffic analysis etc. So, in this paper, we focused on ATM network threats, security service and ATM security mechanisms for threats.
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Many recent studies have been conducted involving the transport of constant and variable bit rate MPEG-2 video in asynchronous transfer mode (ATM) networks. In this study, the traffic control of supporting MPEG-2 video communications in ATM networks under unloaded or loaded network conditions, in which the generated traffic sources are bursty in nature, are considered. We analyse about MPEG-2 traffic and design a model, which makes use of the ATM OAM funcation in order to support the traffic control functions. To implement the model, we propose a scheme, which combines the performance management OAM function and the bandwidth allocation function. Especially, we design this scheme to control the VBR (Variable Bit Rate)MPEG-2 video traffic.
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ATM technology is reaching a certain level of maturity that allow for its deployment in local as well as in wide area networks. Concurrently, audiovisual applications are foreseen as one of the major users of such broadband networks. We present in this paper requriement of real-time multimedia service on B-ISDN networks and simulating the transport of MPEG-2 encoded multimedia data over ATM networks using CBR, VBR, ABR of ATM Traffic Service. We compare each delay time considering network performance and propose need for real-time multimedia service.
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In this paper, we propose a cell scheduling algorithm for ABR traffic in ATM multiplexer. Proposed Algorithm can support ABR service more efficiently than existing WRR and DWRR algorithm. We evaluate the performances of proposed algorithm through computer simulation. Also, we model the VBR and the ABR traffics as ON/OFF source, and the CBR traffic as a Poisson source. And the simulation shows that proposed algorithm better performance over other cell scheduling algorithm in tem of mean cell delay time.
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As multimedia communication services have been widely spreading, the amount of video traffic is rapidly increasing in B-ISDN environment based on the ATM technology. The image quality of MPEG services is very sensitive to the cell losses in ATM network, since each cell contains information needed at decoding process. Since the number of cells in each frame of MPEG is variable, this video smoothing technology need to prepare a buffer for no overflow or underflow at the transmission, requires that some number of cells be taken to the buffer in client before the playback of video. To ensure the high quality image of video, the video smoothing is scheduled by a Group of Picture unit. In this paper, we then apply the theory to reds nightmare encoded in MPEG, and find minimum smoothing buffer size, initial buffer size. It can be used to study the smoothing of stored video.
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일반적으로 교환기에 수용되는 전원장치는 일반 산업용 장비 보다 높은 신뢰성이 요구된다. 특히, ATM 교환기와 같이 회로팩의 고밀집도를 요구하는 시스템에서는 전원장치도 시스템에 부합되는 안정성, 내환경성, 내구성, 고 집적화, 최소화 등의 필수 기술 요건들로 접근되어야 한다. 동시에 ATM 교환기의 수명시간을 보장하기 위한 운용, 유지보수 능력도 만족되어야 한다. 따라서, 본 고에서는 ATM 교환기가 운용중 점검 및 정비가 요구되는 전원장치의 운용유지보수성에 관련된 기술 사항들을 제안한다.
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고속 멀티미디어 데이터를 전송하기 위한 차세대 전송망은 ATM을 기반으로 하는 무선 ATM망에 대해 표준화 동향을 분석하고자 한다. 따라서 본 고에서는 ATM Forum과 유럽 및 미국 일본을 중심으로 무선 ATM 관련 표준화 동향을 분석하고, 현재 각국에서 추진중인 무선 ATM의 구현사례를 조사 분석하였다. 그리고 ATM Forum의 표준화 분석을 통하여 무선 ATM연구 방향 설정의 자료로 활용하고자 한다.
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본 논문에서는 CPU의 역할을 최대한으로 줄이고, 고속으로 트패픽을 정형화 하는 효율적인 정형화기를 설계하였다. 기존에 제시되었던 대부분의 정형화 알고리즘들은 큐를 가지고 CPU에 의해 소프트웨어적으로 트래픽 정형화를 수행하게 된다. 본 논문에서는 주로 하드웨어적으로 정형화 작업을 수행하여 CPU의 부하를 줄여 고속으로 정형화를 수행할 수 있도록 BOP(Bandwidth Oriented Priority) Markovian 정형화기와 Circular 정형화기를 설계하고 시뮬레이션을 수행하였다.
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ATM(Asynchronous Transfer Mode)을 기반으로한 BSC(Base Station Controller)를 이용한 무선 이동통신망에서는 크게 MSC, BSC, BTS로 구성 되어진다. BSC는 MSC(Mobile Switch Center)와의 STM-1급 (155.52Mbps) 정합이 이루어지며, 여러 BTS(Base Transceiver Subsystem)와 T1(1.544Mbps)/E1(2.048Mbps)급 정합이 이루어져 호연결, 관리, 제어 및 MT(Mobile Terminal)의 soft-handoff를 담당한다. BSC내의 저속 가입자 I/F에서는 BTS와 BSC내의 ATM switch와의 정합을 수행하면서 VPI/VCI변환, BSC 내부 cell format으로 변환, 그리고 UPC(Usage Parameter Control)등이 이루어진다. 본 논문에서는 ATM switch를 이용한 BSC 내부의 저속 가입자 I/F의 구현에 관해서 살펴본다.
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Wireless ATM(WATM) intends to provide a broad range of mobile multimedia services through wireless access by mobility extensions from the fixed ATM-based network. Recently, there have been active researches about new handover techniques to support terminal mobility in WATM. In this paper we classify path reestablishment schemes into full reestablishment, path rerouting with a static COS, path rerouting with a dynamic COS, and path extension. For a backward lossy handover procedure, we analyze and compare the performances of path reestablishment schemes in terms of delay, service disruption time and cell loss.
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Generally, in a VOD(video on Demand) system, batching technique is oten used to improve throughput. Since subscribers to VOD servives tend to withdraw their requests as the latency becomes large, an optimal scheduling scheme should consider not only batching size but also withdrawal rae, service latency and fairness between different programs. In this paper, we propose a new scheduling scheme, which shows improvement in fairness and reduction in withdrawal rate and service latency compared with other well known schemes. When there are 2 or more streams are available in the VOD server, proposed scheme apply different program selection policies to each streams. Using this approach effectiveness of stream usage can be improved.
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Wireless multimedia networks require channel allocation strategies for various multimedia traffic since the mobility of users needs to be considered in addition to diversity of QoS requirements of multimedia traffic. In this paper, we propose an Efficient Channel Allocation strategy, based on prioritization of handoff calls used in Guard channel method. Gurad channels can be shared between non real time calls and real time handoff calls. To decrease the probability of handoff failure, when resources become scarce, the Call Admission Control can take some resources away from the active calls. It is shown through extensive simulations that the proposed strategy provides higher channel utilization and lower probability of handoff failure than existing strategies.
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This paper is describing an ADSL access network configuration by packet mode and analyzed the performance of this ADSL network. We are interesting in difference between ATM mode and packet mode concerning to the performance and service availability. So, this paper has described the characteristics of packet mode ADSL network.
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In this paper, we propose an software architecture for home network gateway set-top-box that supports the connectivity between various consumer devices and the Internet simultaneously. To improve the scalability of the software, the proposed architecture uses the abstracted protocol driving structure, and to enhance the user-friendliness, the unified device access and management user interface is implemented using web technology. A prototype for the proposed architecture is implemented for evaluating the usability under the home network test bed.
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This paper presents a method to determine the rolloff factors of both the digital terrestrial TV modulator and the bandpass filter (BPF) at the digital TV receiver input, using an analytical power spectral density model satisfying given co-channel and adjacent channel protection ratios for the digital terrestrial broadcasting services. Since the proposed method is very simple and effective to use, also can be used regardless of type of systems or modulation techniques, this method is expected to be applied to select some other digital terrestrial broadcasting system specifications.
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A new stereoscopic codec. structure using MPEG-2 multiview profile is presented in this paper. In the suggested codec., the left image is coded with motion estimation in the base layerand the right image is coded with disparity estimation in the enhancement layer. Since it is possible to calculate rough motion of the right image sequence with disparity and motion of the left image sequence, motion compensation of the enhancement layer is performed without motion estimation. Since the proposed codec. does not perform motion estimation in the enhancement layer encoding, it is simple and reduces the encoding time. We compared the PSNR of encoded image with three different structured codec., and the experimental results show that suggested codec. has comparable with other codecs.
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To determine the satellite orbital positions under consideration of interference caused by inter-satellite systems is one of the most important issues in terms of optimal usage of satellite network resources. In this paper, we present the orbital positioning method for a new satellite to minimize inter-satellite system interference effect in the fixed satellite communication using a new method. Through the computer simulation, it is clear that the proposed method is suitable to determine the satellite orbital positions.
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The interference evaluation methods and criteria between the analogue TV/FM signals for BSS(Broadcasting Satellite Service) plans and the associated feeder link plans were established in WARC(World Administrative Radio Conference)-77 and 88. However, it should be applied the different interference evaluation methods and criteria of the digital TV signals from those of the analogue TV/FM signals. In this paper, the interference evaluation methods and criteria between the digital TV signals and the analogue TV/FM signals were analyzed. And also, the effects of the interference from the digital signals for Koreasat-1 into the analogue TV/FM signals for Japanese broadcasting satellite were evaluated. The amounts of EIRP reduction in the transmitting space stations were calculated to meet the interference criteria. The results showed that the digital BSS networks including Koreasat-1 would share the limited resources with the analogue BSS networks.
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The KOMPSAT system incorporates multiple missions designed to provide various applications in the field of Korean peninsula observation covering land, sea and coastal zones. The missions are Korea cartography (1:25,000 scale maps of the Korean peninsula), biological oceanography and science instrument accommodation. The operational availability of KOMPSAT TTC system should be predicted more accurately because its failure has a significant influence on satellite command and tracking and on satellite data collection. In this paper, system availability structure of KOMPSAT TTC system are made and availability of KOMPSAT TTC system is analyzed aspect to the system operation in accordance with logistic condition.
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본 논문은 단일 채널에 다수의 정보 신호를 전송하기 위하여 사용하는 PCM/PSK/PM 변조 방식의 전송 신호 대역 특성에 대하여 기술하였다. 위성 관제 신호인 원격 명령 신호 및 원격 측정 신호의 변조 지수에 따라 전송에 필요한 대역폭과 위성과의 거리 측정 신호 전송에 필요한 전송 대역폭을 산출하며, 부 반송파 주파수 사용에 대한 관계를 고찰하였다. PCM/PSK/PM 변조 방식의 대역폭은 위상 변조 지수 1.2 rad 이하에서는 부 반송파 주파수와 전송 데이터 율에 비례한다. 2kbps 원격명령 데이터 전소에 필요한 원격 측정 신호를 위한 부 반송파는 131. 072kHz가 적합하다.
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Toen 방식을 사용하는 거리 측정시스템의 잡음 및 간섭에 대한 열화 도를 분석한다. 위성 링크상의 잡음 및 다중 변조 방식에 의한 전송 신호간 간섭들로 인하여 위상차 측정에 열호가 발생하며, 열화 도는 ranging 측정 시스템의 잡음 대역폭에 의존한다. Ranging 측정 모드에서는 잡음 대역폭 8Hz, 4Hz 그리고 1Hz에 대하여 0.3dB 열화가 방샐하였으며, ranging 및 원격 측정 데이터 전송 모드에서는 대역폭에 따라 6.4dB, 4.2dB, 4dB가 발생하였다.
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본 논문에서는 주파수 영역에서 구현되는 안테나 배열을 이용한 적응형 등화기의 구조를 제안하였다. 제안된 방식은 주파수 영역에서 블록 LMS (least mean squares) 방식을 사용하기 때문에 수렴 속도가 빠르고 계산량이 적다. 또한 안테나 배열을 사용함으로서 다중경로 환경에서 한 개의 안테나를 사용한 경우에 비해 특히 우수한 성능을 지닌다. 다중 경로를 통한 신호들을 분리하기 위해 학습신호를 사용하여 반복적으로 출력신호와의 오차를 최소화하는 방법을 사용하였다. 시뮬레이션을 통하여 안테나의 개수, 신호의 입사각, 세기 등에 따른 성능을 분석하고, 제안된 방식이 다이버시티 시스템에 사용되는 경우에 대하여도 성능을 분석하였다.
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A class of non-parametric detectors based on quantized m-dimensional noise sample space is introduced. Due to assuming the nongaussian noise as a channel model, it is not easy to design the detector through estimating the unknown functional form of noise; instead equiprobably partitioning m-dimensional noise into a finite number of regions, using a VQ and quantiles obtained by RMSA algorithm is used in this paper to design detectors. To show the comparison of performance between single sample detector and system suggested here, Monte-Carlo simulations were used. The effect of signal pulse shape on the receiver performance is analyzed too.
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In this paper, turbo codes with the DC-free trellis codes based on partition chain as constituent codes are presente. And efficient methods to design the DC-free turbo codes are introduced. An iterative decoding with the MAP algorithm is used for the decoding of the turbo codes designed by various methods. As results of simulations, the presented DC-free turbo codes show better error performances than the DC-free trellis codes.
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Carrier recovery, the process of recoverying the carrier in receiver, removes the phase difference between VCO and the received signal. However, the conventional structure of carrier recovery cannot be applied to multi-level QAM demodulator because of the increasing decision interval and the complexity of control as the number of symbol increases. In this paper, we suggest a new carrier recovery algorithm using
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In this article, an algorithm for improving the performance of the convolutional decoder for a COFDM receiver using the subchannel information is introduced. The proposed algorithm defines the average amplitude of the received signal at each subchannel as a certainty of the received signal at that subchannel. If the certainty of a subchannel is low, then the received signal of that subchannel is mitigated, and the brach matric of the convolutional decoder is affected by that signal in a relatively small degree. However if the certainty of a subchannel is high, then the signal is enlarged and the branch matric is affected in a relatively large degree. simulations will show the improved BER performance of a COFDM system when the proposed method has been applied.
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In this paper, a synchronization method of OFDM signals are introduced and its performance is estimated. A proposed method can perform a frame/symbol timing, carrier frequency synchronizations. Reference symbols consist of two duplicate OFDM symbols carrying signals on every sub-carriers. Performances of synchronization under 60GHz millimeter-wave indoor channels are evaluated, which were measured with frequency-sweeping method in common office buildings. A proposed method has improved performances owing to long averaging durations of synchronization metrics in frame/symbol timing, carrier frequency synchronization procedures.
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본 논문에서는 OFDM 시스템에서 사용되는 부 반송파의 수와 동일한 길이의 complementary code를 사용하여 각 부 반송파 데이터를 frequency 영역에서 scrambling하는 PAPR 감소 방안을 제안한다. 이 방법은 부 반송파의 수와 동일한 길이의 complementary code 집합을 이용하여 주어진 데이터에 부과해서 PAPR 값이 가장 적은 complementary code를 사용하여 scrambled된 데이터를 송신함으로서 PAPR 값을 감소시키는 방법이다. 수신기에서의 복호를 위하여 Nc개의 complementary code에 해당하는 log2Nc 비트의 code 인덱스를 데이터와 함께 전송한다. 이때 code 인덱스 비트가 PAPR 값에 영향을 주지 않도록 하기 위하여 CODE인덱스와 데이터가 함께 complementary code로 scrambling되어진다. 제안된 이 방법을 사용하면 주파수 대역효율을 높이면서 PAPR 값을 크게 줄일 수 있다.
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In Korea Telecom, many synchronous optical transmission equipments and its operating terminal (PC) have been operated. However, many equipment operators have requested various supplementary functions such as self-monitoring and taking statistical information. This system has tried to solve the above problems, and therefore to establish centralized monitoring system on synchronous transmission equipments based on telephone office unit.
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In this paper, to reduce BER(Bit Error Rate) in satellite ATM Networks, a new scheme for FEC(Forward Error Corection) using multi-stage Viterbi coder is proposed. In terms of structural complexity, proposed multi-stage Viterbi coder is simpler than the traditional single-stage coder based on the same BER performances. and, through simulation, proposed coder shows excellent error correction capabilities, compared with traditional FEC schemes. Also, we propose a selective FEC mechanism that adaptively changes the number of stages to satisfy the QoS(Quality of Service) requirements. This Selective scheme can be easily implemented using the PLCP(Physical Layer Convergence Protocol) frame structure.
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Since it has been very difficult to collect Korean rain data for winter season, e.g. from November to March, it would be very useful to design satellite communication links if there is a method to extract annual distribution from rain data collected for a specific month. This paper presents a conversion method to annual rainfall rate distribution from rain data for worst month of a year, and illustrates some analysis of the conversion results.
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Providing the connectivity interworking between the lightweight signaling function using in VOD set-top box and the broadband signaling function In the access node system, it can diminish the cost-burden of user about set-top box and we shall use efficiently the network resources. Therefore, In this paper, we shall design the signaling brokerage agent function for the connectivityinterworking in access node system and discuss the result applied its function to the real-time VOD service.
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The high power amplifier (HPA) for broadcasting transmitter systems has nonlinear property in terms of input signal power. Hence, it produces AM/AM and AM/PM modulation to the modulated signal. Therefore, the non-linearity results in bandwidth expansion and nonlinear distortion to in-band signal. In this paper, we propose a simple sain-based predistorter that requires less computational burden and less time for the full initialization of the pre-distorter ROM table.
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This paper proposes a blind multi-user detector using Code-Constrained Minimum Variance (CCMV) method which directly detects the DS-CDMA signals in a multipath fading channel without estimating the channels. This algorithm reduces the complexity of computation by making a small size data matrix with the order of the channel length. Advantageously it requires to know the spreading code and the time delay of only the desired user.
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Software release over the network is the most efficacious way of software update. Software release of electronic switching system, considering its environments, is the typical case that is in need of adopting the method. The media of transferring software and data of TDX-10A electronic switching system are magnetic tapes containing them, so the MT must be delivered between remotely placed office and package generation system. SMART-10A system provides the file tranfer on the data network between TDX-10A and the package generation system and ability of remote application of new software. This paper shows the implementation of file transfer between TDX-10A and computer system connected by data networks, status handling for duplicated system, and monitor process design with IPC on UNIX system.
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This paper specifies the interface and procedures of AINI signalling protocol, which is defined for supporting interworking between ATM public network based BISUP and ATM private network based P-NNI. Also it is discussed in this paper that the required considerations such as message, information element and QoS to design AINI interworking scenario, and evolution direction.
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Modern telecommunications are increasingly demanding the addition of complex switching features to switching system software. These improvements also should satisfy customer demands for quick provisioning of new service features. But whenever we have developed the switching system in various types, we met problems that are lack of system engineers and short developments terms. We need new guidelines of software design to meet the demands and overcome our problems. So we propose new software platform, scenario driven call control engine (SDCCE) for ATM switching system software and implement an effective call control software using scenarios for ATM Switching System. A scenario is a set of procedures and supplementary scenarios written in data structure and gives benefits to easy adapt new or modified function by adding a scenario. The goal of SDCCE is to increase reusability and readability of software. Especially, it gives a good software extensibility and maintainability. And when we developed ptmp call processing control software, we could get high productivity by reusing scenarios and procedures of ptp call processing control software. We applied the scenario driven call control software to ATM switching system.
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In this paper, we present a novel approach named a shared library as an active memory object for application software development of large-scale real-time systems. Unlike the general passive shared memory, shared library proposed in this paper can be activated as an execution object. Moreover this is not tightly coupled with application programs unlike the normal libraries. To implement this mechanism, operating system makes the shared memory as an active object and shared library realizes the indirect call structure. This mechanism enhanced the utilization of main memory and communication performance. And this is successfully applied to the HANbit ACE ATM switching system and the TDX-10 switching system.
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BISDN 망 구축을 위한 ATM 교환기는 고속의 스위치 망을 통해 사용자들의 고속 정보를 교환 할 수 있는 경로를 제공하고 있으며, 기존 통신망들과의 연동을 통해 다양한 서비스를 제공하기 위하여 여러 가지 가입자 정합장치의 수용이 요구되고 있다. 현재 국내에서 개발되어 시험중인 HANbit ACE ATM 교환기는 DS-1, DS-1E, DS-3 및 STM-1급의 가입자 정합 장치를 제공하며, 중계선 정합 장치로는 DS-3 및 STM-1 급을 지원한다. 이러한 구조에서 사용자 QOS 를 만족시키며 네트워크 비용을 최소화 시키는데 많은 어려움이 따른다. 즉 다양한 정합장치와 다단 스위치 구조하에서 다양한 트래픽 특성을 갖는 호/연결에 대한 효과적인 호 수락 제어 기능이 필수적으로 요구된다. 본 고에서는 다양한 정합 장치와 3단 스위치 구조를 갖는 HANbit ACE ATM 교환기를 살펴보고, 다양한 트래픽 수용을 위한 트래픽제어 요구사항을 알아보며, 이와 같은 특성을 해결하고자 실현된 호/연결 수락 제어 기능에 대해 고찰한다.
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ATM 망은 기존 망 서비스를 수용하여야 하며 특히 회선 대행 서비스의 제공은 필수적이다. 회선 대행 서비스는 일정 비트율의 실시간성 서비스이며 손실에 민감한 특성을 갖기 때문에 엄격한 Qos 의 보장을 요구한다. 회선 대행 서비스는 64Kbps 단위의 Time Slot 의 수(N)에 따라 사용 대역폭이 결적되며 ATM 망과 연동을 위해서는 ATM 트래픽 파라메터로 변환되어야 한다. 회선 대행 서비스의 경우 CAS(Channel Associated Signaling)를 사용하는 경우와 Partial Cell Fill을 허용하는 경우에 따라 ATM Cell Rate를 다르게 적용하여야 한다. 이 논문은 ATM 망이 회선 대행 연결을 ATM의 CBR 서비스 카테고리로 Mapping 하기 위한 트래픽 파라메터 산출 방법을 제시한다. 또한 다수의 회선 대행 링크가 하나의 ATM 링크로 다중화되는 경우 ATM 인터페이스의 연결 수락 제어 절차를 제안한다.
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Until now, to solve the problem, the lack of memory at TDX-10A ESS (Electronic Switching System), we have extended only main memory of the systems. However, this method is useful for only Transitcall Processing Subsystems and, it is not an effective way that is able to apply to all Subsystems of ESS because of the financial aspect. In this paper, we will introduce a new method which uses Non-Resident Program. This method utilizes main memory more effectively. We will also analyze the effectiveness resulting from test of new method applied to TDX-10A ESS.
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ETSI(European Telecommunications Standards Institute) 300 34701, ITU-T(International Telecommunication Union) G.965 recommended PSTN, CONTROL, LINK CONTROL, BCC, PROTECTION protocols on V-Interfaces. But it is possible to occur misalignment between LE(Local Exchange) and AN(Access Network), especially in link identification procedure because there isn't any comment about V5.2 system management. In this paper we propose S/W guard timer to improve reliability in V5.2 link identification procedure in scope of Recommendation.
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In this paper, we discuss the CPU Utilization and bottle neck of the router on campus network. Generally, high CPU utilization does not only makes slow network speed but also frequently network disconnection. The above characteristic is based on the network with one router. In order to solve this problem, we reconstruct network configuration with two routers. Our result shows that CPU utilization of network topology with two router have good performance compared to that with one.
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In this paper, we describe an IMT-2000 system architecture, a protocol stack, and basic MAP scenarios(e.g., registration, call delivery) based on the IS-41 and IS-41 and IS-751. This paper focuses on the MAP scenarios to support the IMSI which is defined for the global roaming between GSM and IS-41 Networks through the Family of System approach. This paper also deals with the design of the MAP protocol stack transported over the ATM networks and introduces the software structure of MAP in IMT-2000 MSC.
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Controlled transfer (CT) capability, a new ATM transfer capability (ATC) for high-speed data applications which using credit-based flow control, has recently been proposed and studied in ITU-T. In this paper, we review the existing dyanmic buffer allocation schemes and propose an improved scheme. Also, we compare the performances of the existing buffer allocation methods such as static allocation, flow controlled virtual channels (FCVC), and zero queueing flow control (ZQFC) with the proposed method through simulation. Simulation results show that the proposed scheme exhibits a better performance than the existing schemes in terms of throughput, fairness, queue length and link utilization.
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This paper evaluates the VSN(Virtual switch Network) characteristics in the internal call processing of IMT-2000 switching system, which is composed of VSN instead of ATM switch network. In results, internal call establishment delay is increased approximately 5.4msec than the conventional ATM switching system. The evaluated condition is the load 0.8, and the 100km distance between VSNs. It is confirmed that the VSN has the potentiality in the practical implementation.
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The disks containing all the system software-OS(Operating System), application program, and DB(Data Base)-happen to be broken. This happens not only to general computer systems but also to electronic switching system. In the electronic switching system, this causes the essential data and software needed for operating the system to be damaged and is fatal to services, so that they should be recovered as soon as possible. Especially the data, having the information of subscriber, trunk, prefix, and system configuration should be receovered preferentially. To manage this situation, the system should let the operator know that the data are damaged and recover the damaged data. This paper shows a way of recovering this damaged data, the object data of audit, the structure of DBMS and the implementation of audit in the case of the domestic high capacity electronic switching system, TDX-10A.
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This paper proposes a new Asynchronous Transfer Mode(ATM) switch architecture for the Broadband ISDN. The proposed switch has the architecture to prohibit the out-of-sequence in shared buffer switch system with being fixed buffer size in the out-buffered large scale ATM Switch System. then in this paper proposes cell resequence algorithm to decrease the out-of-sequence problem. also, we studied the out-of-sequence problem that was occurred by the cell transfer delay and the cell overflow due to the fixed buffer size when cell resequenced and we propose to implement optimal ACFIFO(Address Counter First In First Out) buffer size which has the minimized cell loss.
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As user's demands for high-speed data traffic are recently increased, ABR services are considered as one of important service requirements in ATM networks. Unfortunately, a number of existing ATM switching systems have structural drawbacks as to support ABR services because these switching systems have been developed to support realtime(rt) services such as CBR and rt-VBR services. To support ABR services in the existing ATM switching systems, new traffic control mechanisms for ABR services are required. This paper proposes a method for supporting ABR services in ATM swithcing systems without back-pressure mechanisms and evaluates the performance of the proposed method using simulation.
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The multimedia services like video-conferencing and interactive multimedia services require the support for the multipoint-to multipoint connections from the networks. The routing and signaling protocols for supporting these connections in ATM networks have been a interesting topics in the Telecommunication standardization sector such as ATM-Forum. In this paper, we survey and discuss the various well-known switching algorithms for multi-way communication.
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In this paper, we present mSROS(Micro-Scalable Realtime Operating System) to be applied commonly to the device controller systems in the HANbit ACE256 system. The device controller systems in HANbit ACE256 system are organized as many kinds of device controller. Applying modified PPOS(Peripheral Processor Operating System)which is an operating system for devices of the TDX-10 switching system to the firmwares for them, the inefficiency in development and maintenance exists inherently. To remove the inefficiency nd to improve the performqance of firmwares, we build a common operating system platform that including multi-tasking microkernel so that the firmwares among devices can acquire convenient development and cheap cost of maintencance. Especially, building a virtual machine as a development methodology, it is possible to remove dependency from the kernel so that any kinds of commercial real-time kernels can be used in mSROS as a basic kernel. The virtual machine in mSROS is compatible with the API of SROS(Scalable Realtime Operating System), PPOS, and CROS(Concurrent Realtime Operating System).
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This paper describes an interconnection network structure which transports information among processors through a high speed ATM switch. To efficiently use the high speed ATM switch for the message-based multiprocessor, we implemented the cell router that performs multiplexing and demultiplexing of cells from/to processors. In this system, we use the expanded internal cell format including 3bytes for switch routing information. This interconnection network has 3 stage routing strategies: ATM switch routing using switch routing information, cell router routing using a virtual path identifier (VPI) and cell reassembly routing using a virtual channel indentifier (VCI). The interconnection network consists of the NxN folded switch and N cell routers with the M processor interface. Therefore, the maximum number of NxM processors can be interconnected for message communication. This interconnection network using the ATM switch makes a significant improvement in terms of message passing latency and scalability. Additionally, we evaluated the transmission overhead in this interconnection network using ATM switch.
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When the information of announcement facility is modified or added, they are recorded on a tape and then are updated manually using the cassette tape recorder at each office. But the degrade of the tone quality owing to repeated use of the tape and some recording mistakes by processing manually deteriorate the quality of service. And new services such as IN(Intelligent Network) and added functions make the announcement changed very often. Therefore the improved skill of the announcement handling is needed. This paper introduces the implementation of the TDX-10A on-line recording function of transferring voice in PCM data file and storing it in the memory of the recorded announcement facility, when message is recorded onthe fixed type of announcement facility.
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The Phone Voting service allows subscribers to propose a voting through a telephone, and enables them to survey public opinion using telephone network. The demand on this service is growing faster and demands will be increased much more. It makes the bust traffic at the Toll SSP system on Intelligent Network because of the temporary bust traffic congestion on the Toll SSP compared to the normal call traffic. This paper will show what the problems and the causes are, and how we can solve them. The solution to these problems is an implementation of the SSP function on the Local Excange for the PV service.
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이 논문에서는 ITU-T E.164 및 AESA ICD/DCC 주소체계 및 형태를 비교분석하고, 공중 ATM 망에서 ITU-T E.164 주소체계외에 AESA ICD, DCC 주소체계를 수용할 경우 E.164 및 AESA ICD/DCC 주소형태(format), AESA ICD/DCC 주소체계를 사용한 망 계획 및 ATM 망에서 이러한 주소체계를 수용하여야 하는 이유를 분석하였다. 그리고 공중망 및 사설망을 포함한 전체 ATM 망에서 AESA ICD/DCC 주소체계를 사용할 경우 AESA ICD/DCC 주소형태(format)에 포함되어야 하는 서브 계위(hierarchy)와 이들을 사용한 망 계획 방안을 제시하였다. 본 논문에서 제시한 내용은 AESA ICD 주소체계를 수용할 경우에도 유사하게 적용되어야 할 것으로 판단된다.
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This document introduces MPC(Multiple Point Code) capabilities which has been implemented in the TDX-series exchanges as well as LGIC"s exchanges and describes the interaction with domestic CCS7 specifications. Additionally, this document introduces MPC capabilities used in American signalling networks and reviews the general usability of MPC. MPC.
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B-ISDN에서 교환 노드로서 동작하게 될 ATM 교환 시스템은 사용자 단말이 ITU-T 신호 권고안을 사용하는 단말과 ATM Forum 신호규격을 사용하는 단말이 공존할 수 있다는 전제하에 모든 신호 프로토콜을 다 수용할 수 있는 호/연결 제어 소프트웨어가 요구된다. 따라서 이 논문에서는 ITU-T 신호 프로토콜과 ATM Forum 신호 프로토콜에 대하여 신호 메세지, 정보 요소, 신호 능력을 비교 검토하여 정리하였다. 이 비교 검토 결과에 따라서 ITU-T 1.2931, 1.2971, ATM Forum UNI3.1 신호 프로토콜을 처리하는 기능 블럭과 UNI4.0 신호프로토콜을 처리하는 기능 블럭을 분리하여 신호 프로토콜을 처리하도록 가입자 호/연결 제어 소프트웨어를 구현하였다.
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Inspired by the principle of the open market, a future network service model is forced to permit a much greater degree of flexibility, reconfigurability, programmability, protability and maintainability in telecommunication infrastructure. In this paper, one of standardization activities for the open programmable network model, IEEE standardization project P1520 (Application Programming Interfaces for Networks), is discussed.
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A 20 GHz 2-stage MMIC (Monolithic Microwave Integrated Circuits) LNA(Low Noise Amplifiers) has been designed. The pHEMT with gate length of 1.15 um has been used to provide ultra low noise and high gain amplification. Series and Shunt feedback circuits were interted to ensured high stability over frequency range of DC to 60 GHz. The size of designed MMIC LNA is 2285um x 2000um(4.57mm2). The simulated noise figure of MMIC LNA is less than 1.7 dB over frequency range of 20 GHz to 21 GHz.
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A LNA(Low Nosise Amplifer) module for the Ka-band satellite transponder has been developed, which is composed of developed two MMIC chips and 50
$\Omega$ line. This LNA exhibited noise figure less than 3.12dB, linear gain higher than 32dB from 30.085GHz to 30.885GHz frequency range. Temperature test from$20^{\circ}to$ $60^{\circ}C$ of the LNA Module showed very small noise figure and linear gain variation of 0.2 dB and 0.4dB. -
A 2watts MMIC(Monolithic Microwave Integrated Circuits) SSPA(Solid State Power Amplifiers) for 20GHz band communication systems has been designed, manufactured and measured. The 0.15um pHEMT technologywith the gate size of 400um for single device was used for the fabrication of MMIC Power Amplifier chips. The precision MIC patterns for the peripherals like power combiner/divider and microstrip lines were realized using hard substrate for gold wire/ribbon bonding. The measured data shows that this MMIC SSPA has the linear gain of 18dB, output power of 33.42dBm(2.2Watts)at 20~21GHz.
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In this paper, we have presented an improved design of the microwave level meter based on the principle of FM-CW radar. First, we have analyzed the effect of VCO nonlinearity on the spectral broadening of the beat signal, and presented a new type of design theory to linearize VCO tuning curve adopting FFT algorithm. Simulation results for a VCO having the linearity of 25% have been presented, which show the usefulness of the design algorithm.
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This paper presents calculated results for the infinite phased arrays of the probe-fed rectagualr microstrip patches. A numerical model that is based on a rigorous Green's function and galerkin solutionsis is described. In an arbitrary scan plane, the input impedance and the input reflection coefficient versus the scand angle are calculated. The effects of substrate parameters on the phased arry antenna are considered. The scan blindness phenomenon due to the surface wave is observed and the input impedance bandwidth in the arbitrary scan plane is calculated.
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The stacked microstrip patch antenna is modeled by a simple cavity model. Using this model, the input impedance of the stacked microstrip patch antenna fed by a coaxial probe is expressed as a function of antenna paprameters and frequency. We calculate the input impedance of the stacked microstrip patch antenna for the variation of frequency.
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In this paper a radiation problem for a finite microstrip antenna structure is analyzed. For the analysis of finite structures we utilize the equivalent volume current. Intergral equation for the unknown equivalent volume current induced on a finite microstrip structure is derived and solved by the use of conjugate gradient-fast fourier. transform (CG-FFT) method. Some numerical examples are radiation patterns derived by the equivalent volume current solved by the conjugate gradient-fast fourier transform.
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본 논문에서는 최근 광대역 무선 가입자망으로 각광받고 있는 LMDS(Local Multipoint distribution Service)시스템에서 Head-End 의 AIU(Air Interface Unit)와 HUB 사이의 거리에 따른 전송지연 시간과 HUB 와 가입자 장치(CPE:Customer Premises Equipment)내의 NIU(Network Interface Unit)간의 전송 지연 시간에 의하여 서비스 반경이 제한되어 지는 것에 관하여 살펴보고 적절한 서비스 반경에 대하여 제안하였다.
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In this paper, we measured inter-floor loss in multifloored building to surround buildings at 910MHz. Effect of interfloor diffraction to propagate through out-surface were smaller than effect of reflection of surrounding buildings. If multifloored building were offered W-PBX service, we will have to design optimization of indoor cell to overcome time delay difference.
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This paper investigate the interaction of electromagnetic fields(EF's) in the human head with respect to the radiated waves from 1.8〔GHz〕 PCS terminal that the titled angles of a monopole antenna between the head and the horizontal axis of the terminal are 45, 60, 75 and 90 degrees respectively. And then, it is found the fact that the induced SAR distri bution in the model of the head gradually decreases by in creasing the titled angle.
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The electromagnetic properties of leaky-waves guided by metal-strip grating configurations can be phrased in rigorous modal theory. Such a modal solution expressed by simple electrical transmissionline networks is utilized to analyze the leakage and filtering characteristics of metal-strip gratings. In particular, the modal transmission-line theory can serve as a template for computational algorithms that systematically evaluate the radiation effects that are not readily obtained by other methods.
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High frequency scattered fields by a double impedence wedge are computed. In the procedure of the computation, arbitrary impedence faces and wedge angles are considered. The diffraction coefficients for the single, double and triple diffraction mechanism are founded. The second-order and third-order diffracted fields are approximated via the extended spectral ray method and the modified Pauli-Clemmow method of the steepest descent. The maliuzhinets function which is very difficult to obtain accurate value is approximated by the Volakis's asymtotic expression. Numerical computations are performed for the various wedge angles and surface impedence values.
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크기가 작은 구의 전파흡수체의 설계 방법을 제시하였다. 산란현상을 물리적인 관점에서 보면 크기가 작은 구의 역산란파는 반사파뿐만 아니라 회절파에 대한 영향을 함께 고려하여야 한다. 본 방법으로 구한 전파흡수체를 크기가 작은 구에 코팅하였을 경우 기존의 무한 평면으로 가정하여 구한 전파흡수체 보다 우수한 흡수 성능을 보인다.
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The Scattering of arbitrarily shaped gratings covered with dielectric slab is considered. The total field in each region is expressed in terms of incident field and scattered field by induced currents on the surface of the grating. Some numerical results is presented nd compared with previous ones in cases of several gratings.
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Scattering of TE waves by a periodic conducting surface with dielectric cover is considered. A method for the aalysis of scattering from periodic structures based on the numerical solution of the integral equations is further developed. Using periodicity (Floquet's theorem), the range of the integral equations is reduced to a single period where the kernels are the Green's functions for periodic arrays. The numerical solution of the intergral equations is obtained using the method of moments. From numerical results for the reflected power the effects of surface profile shape, period-to-depth ratio, and cover permittivity on the scattering behaviors are examined.
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접지된 유전체층 위에 위치한 스트립 격자구조에 TM 편파된 입사파가 입사할 경우 전자기 산란문제를 특성 모드 이론으로 해석하였다. 몇 개의 특성 모드전류로부터 원거리 산란패턴을 구하여 blazing 현상과 같은 산란특성과 특성모드 패턴과의 연관성을 관찰하고, 기존의 결과들과 비교하여 특성모드 해석방법의 타당성을 검증하였다.
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An application determination of the dominant-mode fields in ridge waveguides at all frequencies has been made. Evaluations of the fields along the walls of a commercially standard single-ridge guide having a usable frequency range from 3.75 to 15.0 Gc, This paper presented the analysis of the mode directive coupling characteristics of two ridge waveguide using mode matching techniques for TE10 mode.
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We propose comb-line filter using SIR(Stepped Impedance Resonator) with two transmission line. The coupling structure of the filter is double coupled line where two coupled lines are linked with cascade. We find out the inverter function of the filter. using even and odd mode impedance. The merits of the filter are that first, we can design transmission zero point at any frequency that we wanted without using lumped elements : chip capacitors and inductors. Second, we can design small size filters. To validate the inverter function of the filter with double coupled line we designed and fabricated two-pole band pass filter with the proposed filter structure.
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Telecommunication system demands for increased bandwidths and operating frequencies for analog signal processing could be satisfied in the near future by the emergence of a novel technology based on magnetostatic waves propagating in low loss ferrimagnetic films. The magnetostatic wave n the only available technology for analog signal processing directly at microwave frequencies.
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In this paper, the design, fabrication, and experiments of linearly tapered slot antenna(LTSA) with uniplanar microstrip-to-coplanar strip(CPS) line transitions are presented. The effect of reducing and increasing with taper width G teper longth 1, and opening angle are also mesured at 10 GHz.
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In this paper, we present robust reliable
$H\infty$ controller design methods of continuous and discrete uncertain time delay systems through LMI(linear matrix inequality) approach, respectively. Also the existence conditions of state feedback control are proposed. Using some changes of varables and Schur complements, the obtained sufficient conditions are transformed into LMI form. We show the validity of the proposed method through numerical examples. -
Generally, the principle function of simulator control loading system is to provide the pilot or student with the "feel" of the actual aircraft flight control systems during flight, taxing, and in malfunction. Flight control "feel" is the resistance felt by the pilot when moving a control stick or pedal, coupled with the amount of control surface deflection, and hence aircraft response, resulting from the input. Therefore, the control loading servo must be capable of performing to some general list of requirements derived from real aircraft control forces. In this paper, we deal with a
$\mu-controller$ design for a control loading system of the flight simulator. For this, we derive a frequency response of the hydraulic system from the identification data and then design a controller using a$\mu-synthesis$ method. Under the same condition of simulation,$\mu-controller$ provides the superior performance than PID controller.than PID controller. -
In this paper, we present an
$H^2$ controller design of RTP(rapid thermal processing) systems satisfying robust stability and performance using weighted mixed sensitivity minimization. In industrial fields, RTP system is widely used for improving the oxidation and the annealing in semiconductor manufacturing process. The main control factors are temperature control of wafer and uniformity has been solved by PID control method. Because the reference inputs of RTP are ramp, we improve performance of RTP system by the design of$H^2controller$ using the weighted mixed sensitivity function. Also we compare$H^2controller$ with PID controller in terms of performance. An example is proposed to show the validity of proposed method. -
Sensitivity and calibration considerations are most important in the design and implementation of real control systems. Ideally parameter changes due to various causes should not appreciably affect the system's performances. But all the values of physical components of the plants and controllers as well as the relevant environmental conditions change in time, thus the output performance can be deteriorated during the operating span of the system. Naturally the duty of calibration or the prevention of performance deterioration due to excessive component sensitivity should be provided to the control system. In this paper, we propose a digital controller which has the capability of calibration and gain adjustment as well as the execution of control law. Specifically the problems of gain adjustment and offset calibration in the light source and CdS sensor module for position measurement in a flexible link system are considerably resolved. The parameters of measurement module are prone to change due to environmental brightness conditions resulting in poor steady state performance of the overall control system. Thus a proper method is necessary to provide correction to the changed values of gain and offset in the position measurement module. The proposed controller, whenever necessary, measures the open-loop characteristics, andthen calculates the offset and sensor gain correction values based on the prepared standard measurements. It is applied to the control of a flexible link system with the gain and offset calibration porblems in the light sensor module for position to show the applicability.
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A heuristic sweeping algorithm for an autonomous smearing robot which executes the area filling task is proposed. This algorithm searches tracking points with the obstacle andenvironment wall while the robot tracking whole workspace, and finds sequential tracking line by sequentally connecting the tracking points in such a way that (1) the line should be never crossed, (2) the total tracking points should be is linked as short as possible, and (3) the tracking link should be cross over the obstacle in the work-space. If the line pass through the obstacle, hierarchical collision free algorithm proposed is implied. The proposed algorithm consists of (1) collision detection procedure, (2) obstacle map making procedures, (3) tracking points generation procedures for subgosls, (4) tracking points scanning procedures, and (5) obstacle avoidance procedure.
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본 논문에서는 지역최소점에 도달하는 문제가 발생하지 않으며 빠르고 간편한 방식으로 로보트의 장애물 회피를 할 수 있는 윈도우 분석법을 이용한 새로운 장애물 회피와 경로계획 알고리듬 알고리듬을 제안한다. 미지의 경로상에서 장애물 윈도우에서의 특징을 이용하여 안전한 주행 경로를 선택하며, 장애물 회피를 한다. 시뮬레이션의 결과를 통하여 이 방법의 신회성과 우수성을 입증한다.
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This paper proposes a new fuzzy controller using variable structure control theory. In this paper, after the time-varying fuzzy sliding surface is designed, the fuzzy rules are defined based on the variable structure control theory. This design method makes the fuzzy controller design more structured and can guarantee the stability and robustness of the fuzzy controller and overcome the shortcoming of the variable structure system. Through computer simulation and experiment of nonlinear inverted pendulum system, this thesis demonstrate that system has the robustness against disturbance and modelling error, and the tracking performance of it is improved.
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This paper is to design stable fuzzy controller so as to control chaotic nonlinear systems effectively via fuzzy control system and Parallel Distributed Compensation (PDC) design. To design fuzzy control system, nonlinear systems are represented by Takagi-sugeno(TS) fuzzy models. The PDC is employed to design fuzzy controllers from the TS fuzzy models. The stability analysis and control design problems is to find a common Lyapunov function for a set of linear matrix inequalitys(LMIs). The designed fuzzy controller is applied to Rossler system. The simulation results show the effectiveness of our controller.
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The objective of this paper is to design a adaptive fuzzy controller for autonomous navigation of mobile robot. The adaptive fuzzy controller has an advantage in data processing time and convergence speed. The basic idea of control is to induct membership function and fuzzy inference rules and to scale inducted membership function to suitable robot state. The adaptive fuzzy control method is applied to mobile robot and the simulation results show the effectiveness of our controller.
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In this paper, the design method of fuzzy neural network(FNN) controller using indirect adaptive control technique is presented for controlling chaotic nonlinear systems. Firstly, the fuzzy model identified with a FNN in off-line process. Secondly, the trained fuzzy model tunes adaptively the control rules of the FNN controller in on-line process. In order to evaluate the proposed control method, Indirect adaptive control method is applied to the representative continuous-time chaotic nonlinear systems, that is, the Duffing system and the Lorenz system. Simulations are done to verify the effectivencess of controller.
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In this study, the basic image-board and algorithm has been developed to extract a road lane by modeling the driving process. The high speed processing enables an image capture, processing and prompt decision making. In order to high speed processing ASIC like FPGA was designed and integrated in one board system. The algorithm enabling road driving must recognize a straight and bend edge separately. The high speed image processing board using FPGA can be used in real-time decision makeing system for road driving and in the machine vision under bad working environments like a coal mine. And it also can be used in the safety control system in subway and in image input system of CCTV and CATV by designing the board to meet various user's needs.
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컴퓨터 그래픽스 기술의 발전과 더불어 인체의 움직임을 사실적으로 구현하기 위한 연구가 활발하게 진행되고 있다. 본 논문에서는 인체의 동력학적 특성을 고려한 실시간 애니메이션이 가능하도록 인체를 모델링하였다. 인체의 동력학적 특성을 해석하기 위하여 인체를 16 자유도를 갖는 강체(rigid body)로 가정하였으며 Branch 형태의 복잡한 기구학적 형상을 가진 인체를 5개의 단순한 형태의 기구학적 연결체로 분할 하여 모델링을 수행하였다. 이러한 동력학 모델은 단순히 기구학 만을 이용하는 경우보다 사실적이면서도 실시간으로 애니메이션이 가능하다. 이와 같이 동력학적 모델을 사용하여 애니메이션을 수행할 경우 부가적인 장비를 사용하지 않고도 다양한 형태의 인간 움직임을 사실적으로 모사할 수 있다.
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Recently, the research of the FPD(Flat Panel Display)which is substituted for CRT(Cathode Ray Tube) has been widely progressed. But most equipment that are used for production of FPD are expensive and we must import these equipment. Among these equipment, most important one is a auto-alignment system. In this paper, we present a high speed, high precision auto-alignment system, in which a PLD auto tuning algorithm, 1-dimensional CCD(Dcharge Coupled Device) camera, vision board, and vision data processing algorithm are included.
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본 논문에서는 메시지 패싱 전송을 기반으로 하는 병렬 처리 시스템의 상호연결망 구조와 특성을 조사하고 비교한다. 특히, 상용 시장에서 널리 알려진 대표적인 병렬 처리 시스템의 상호연결망 특성과 ETRI에서 개발된 고속 병렬 컴퓨터(SPAX)의 계층 크로스바 상호 연결망(Xcent-Net) 특성을 상호 비교한다. 메시지 패싱 전송 기반의 상호연결망은 일반적으로 확장성이 우수하여 대규모 병렬 처리 시스템을 구축하는데 유리하다. Cray T3E 시스템, Intel ASCI TFLOPS 시스템, Tandem Himalaya S70000 시스템, IBM RS6000 SP2 시스템등은 메시지 패싱 상호연결망을 기반으로 수백개에서 수천개의 대규모 프로세서를 연결한 병렬 처리 시스템이다. ETRI SPAX 시스템은 Xcent-Net 메시지 패싱 상호연결망을 기반으로 최대 256개 프로세서를 연결한 고속 병렬 처리 시스템으로 우수한 확장성과 높은 성능을 제공한다. 본 논문에서는 상호연결망의 구조와 함께 라우팅 스위치 구조 및 특성을 중심으로 전송 지연시간, 그리고 노드당 전송 대역폭 특성을 비교한다.
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In this paper, we propose a matrix star graph which improves the network cost of the well-known star grah as an interconnection network. We analyze its characteristics in terms of the network parameters, such as degree, scalability, routing, and diameter. The proposed matrix star graph MS2,n has the half degrees of a star graph S2n with the same number of nodes and is an interconnection network with the properties of node symmetry, maximum fault tolerance, and recursive structure. In network cost, a matrix star graph MS2,n and a star graph S2n are about 3.5n2 and 6n2 respectively which means that the former has a better value by a certain constant than the latter has.
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In this paper, we consider the problem of optimal broadcasting in recursive circulants under multi-port communication model. Recursive circulant G(N, d) that is defined to be a circulant graph with N vertices and jumps of powers of d is a useful interconnection network from the viewpoint of network metrices. Our model assumes that a processor can transmit a message to
$\alpha$ neighboring processors simultaneously where$\alpha$ is two or three. For the broadcasting problem, we introduce 3-trees and 4-trees. And then we show that 3-trees and 4-trees are minimum broadcast trees in 2-port model and 3-port model. Using the above results, we show that recursive circulants g(2m, 2) have optimum broadcasting time in 2-port model and 3-port model. -
The matrix hypercube MH(2,n) is the interconnection network which improves the network cost of the hypercube. In this paper, we propose an algorithm for one-to-all broadcasting in the matrix hypercube MH(2,n). The algorithm can broadcast a message to 22n nodes in O(n) time. The algorithm uses the rich structure of the matrix hypercubes and works by recursively partitioning the original matrix hypercubes into smaller matrix hypercubes.
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Whether a given tree is a subgraph of the interconnection network topology is one of the important problem in parallel computing. Trees are used as the underlying structure for divide and conquer algorithms and provide the solution spaces for NP-complete problems. Complete binary trees are the basic structure among those trees. Binomial trees play an important role in broadcasting messages in parallel networks. If binomial trees can be efficiently embedded in complex binary trees, broadcasting algorithms can be effeciently performed on the interconnection networks. In this paper, we present average dilation 2 embedding of binomial trees in complete binary trees.
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In parallel system, the execution times of tasks cannot be accurately estimated and tasks may arrive at any time. In case, processors are overweighted with workload, the system utilization deteriorates. To solve this problem, dynamic load balancing that rearranges tasks in overloaded processors is required. We prospose the improved dynamic load balancing algorithm for
$\textsc{k}-ary$ n-cubes using the property of ring and MWA which is the dynamic load balancing one for mesh. The proposed algorithm which uses the global load information has less communication cost than GDE, DDE and load difference within 1. -
In this paper, we describe a method for two-way communication service for smart phone integrated with pager which receive various kinds of Internet service information and pushes this information into smart phone to make it available for Internet assess. In this method, the server can push the status data of message boxes into the smart phone and it makes connection to the server automatically. The proposed method will make it possible to manage and excange the information and resources in an efficient manner during idle time, and will provide the potential capabilities of developing a variety of new Internet services for the system.
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This paper describes the design and implementation of file system which allows the collaborative computing in mobile environment. The design goal is to make a logically one file system in the distributed computer systems. The characteristics of frequent, foreseeable and variable disconnections in a mobile environment wrer taken into consideration. We introduce an auto-hoarding system that provides the availability of large number of nodes which are weakly and intermittently connected. The data consistency problems in distributed or replicated mobile data are also discussed.
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Mobile computers have restrictions for size, weight, and power consumption that are different from traditional workstations. Storage device must be smaller, lighter. Low power consumed storage devices are needed. At the present time, flash memory device is a reasonable candidate for such device. But flash memory has drawbacks such as bulk erase operation and slow program time. This causes of worse average write performances. This paper suggests a storage method which improves write performance.
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Most popular disk block replacement polices are LRU(Least Recently Used)policy and LFU(Least Frequently Used)policy. The LRU policy replaces blocks according to the most recent reference without considering the frequency of reference. The LFU policy replaces blocks according to the frequency of reference without considering the recently of the reference. In this thesis, a policy called LFR(least Frequently Use & Not Used Recently) disk block replacement policy is presented. The LFR policy subsumes the LFU policy and the NUR policy. The spectrum of the LFR policy exists between the LFU policy and the NUR policy because we co give different weight to each reference of a block. The implementation shows LFR policy outperforms the previously implemente LRU policy.
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본 논문은Multimedia video processor로써 멀티미디어 데이터, 특히 비디오데이타 처리에 적합?록 구성되어 있는 프로세서이다. TMS320C80에 Multimedia OS를 사용할 경우에 효율성의 타당성을 검증하기 위하여 영상처리를 3가지 방법으로 수행시켜 그 결과를 비교한다. 채택한 영상처리로 DCT와 2차 Laplacian을 채택하였고 이를 적용하는 방법은 첫째, 일반적인 순차적으로 수행하는 방법과 둘째 기본으로 제공되는 kernel의 규약을 따르는 방법, 셋째로 OS모델을 따르는 경우의 방법으로 연산한다. 이 결과 첫번째 두번째 세번째 경우의 순서로 효율이 높은 결과를 얻었다. 이는 구현 방법이 복잡한 응용에 사용되어질 경우, OS모델이 우수할 것임을 반증한다. 이와 같은 결과를 토대로 TMS320C80에 적합한 task managing 부분의 OS kernel model을 제시한다.
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In this paper, a novel test method is proposed to detect hard and soft fault in CMOS operational amplifiers. Proposed test method mark use of the offset character, which is one of the op-amps characteristics. During the test mode, CUT is implemented to unit gain op-amps with feedback loop. When the input is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage exceeding predefined range of tolerance. Using the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time is reduced. The accuracy and effectiveness of the method is verified through HSPICE simulation.
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This paper proposes efficient methods that integrate and execute local plan rules of task agents in a multi-agent environment. In these methods, each agent's plan rules are represented in a network structure, and these networks are then collected by a single task agent to build a integrated domain network, which is exploited to achieve the goal. Agent problem solving by using the domain network enables a concurrent execution of plan rules that are sequential in nature.
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This paper describes a direct transfer method of multimedia data stream between multimedia processor and network device without using system memory. The hardware architecture and functions for direct transfer, the method to transfer multimedia data to and from the multimedia processor and etc are described. Comparing the proposed method with general methods, I show that the direct transfer method can decrease number of bus accesses and bus cycles.
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The Constructive Battle simulation Model is very important to the recent military training for the substitution of the field training. However, real battlefield systems operate under rea-time conditions, they are inherently distributed, concurrent and dynamic. In order to reflect these properties by the computer-based simulation systems which represent real world processes, we have been developing constructive simulation model for several years. The constructive simulation system is one of the famous real-time system software, nd the one common feature of all real-time systems is defined as the correctness of the system depend not only on the logical result of computation, but also on the time at which the results are produced. Conventionally, scheduling and resource allocation activities which have timing constraints are major problem of real-time computing systems. To overcome these constraints, we elaborated on these issues and developed the simulation system on commercially available hardware and operating system with lock-free resource allocation scheme and rae monotonic scheduling.
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In an ongoing project at ETRI-CSTL, A debugger for distributed programs that run on a varied collection of machines is being built. To build such debugger, a clientserver model is incorporated. This strategy enables us to provide a unified user interface and isolate debugger core from the user interface. Several debugging servers running on a diverse set of platforms permit the implementation of a distributed debugger for heterogeneous environment, and the single debugging client provides unified debugging concept and graphical user interface over various servers. Also, the precise specification of the interaction protocol between the client and server facilitates client to be paired with a variety of server implementantations. This paper describes the design and implementation of our debugger, concentrating on the system architecture.
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In this paper, a transformation-based English part of speech tagging system is designed and implemented. The tagging system tags raw corpus at first and the transformation rule correct the errors. Apart from traditional rule based tagging system, this system makes rules automatically. Using 60,000 words of corpus as a training corpus, the transformation rules are generated automatically by iterative training. The idea how to calculate positive effect of transformation and select transformation rules is proposed to generate more effective and correct transformations. In this paper, part of the Brown corpus and English text is used for experimental data. And the performance of transformation based tagging system is demonstrated by the calculation of accuracy.
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The electrical characteristics of NMOSFETs with asymmetrical source/drain regions have been expermentally investigated using test devices fabricated by
$0.35\mu\textrm{m}$ CMOS technology. The performance degradation for asymmetric transistor and its causes are analyzed. The parasitic resistances, such as series resistance of active regions and silicide junction contact resistance, are distributed in parallel along the channel. Depending on source/drain geometry, the array of those resistances is changed, that results the various electrical properties. -
A MESFET device with double
$\delta-doped$ channel is designed and investigated by computer simulation. The device with optimized design parameters such as a doping ratio and a spacer thickness, shows superior performance to conventional MESFETs. The effects of the FWHM of$\delta-doped$ layers device characteristics are investigated to account for the thermal process -
A SiGe p-channel MESFET using
$\delta-doped$ layers is designed and the considerable enhancement of the current driving capability of the device is observed from the result of simulation. The channel consists of double$\delta-doped$ layers separated by a low-doped spacer which consists of Si and SiGe. A quantum well is formed in the valence band of the Si/SiGe heterojunction and much more holes are accumulated in the SiGe spacer than those in the Si spacer. The saturation current is enhanced by the contribution of the holes inthe spacer. Among the design parameters that affect the performance of the device, the thickness of the SiGe layer and the Ge composition are studied. The thickness of$0~300\AA$ and the Ge composition of 0~30% are investigated, and the saturation current is observed to be increased by 45% compared with a double$\delta-doped$ Si p-channel MESFET. -
Thin film SOI(Silicon-On-Insulator) devices exhibit floating body effect. In this paper, SOI NMOSFET is proposed to solve this problem. Some part of gate oxide was considered to be 30nm~80nm thicker than the other normal gate oxide and simulated with TSUPREM-4. The I-V characteristics were simulated with 2D MEDICI mesh. Since part of gate oxide has different oxide thickness in proposed device, the gate electric field strength is not the same throught the gate and consequently the reduction of current kink effect is occurred.
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Recently, the gate oxide damage induced by the plasma processes has been one of the most significant reliability issues as the gate oxide thickness falls below 10 nm. The process-induced damage was studied with the metal antenna test structures. In addition to the electron trapping, the hole trapping in a 10 nm thick gate oxide due to the plasma-induced charging was observed in the NMOS's with a metal antenna. The hole trapping gave rise to the decrease of the transconductance (gm) similarly to the case of the electron trapping, but to the extent much less than the electron trapping. It would be because the electrical stress that the plasma-induced charging forced to the gate oxide for the devices with the hole trapping was much smaller than for those with the electron trapping. This hypothesis was strongly supported by the measured characteristics of the Fowler-Nordheim current in the gate oxide.
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The 1-D numerical model and its extraction methodology are suggested and these simulation results for the S-swing as a function of back-gate voltage are well matched with the measured. S-swing characteristics are analyzed using PD-SOI devices with enough deeper regions up to substrates. The PD-SOI device doesn't have to be short channel to see the anomalous subthreshold phenomena based on the back gate bias. This results recommend to operate better SOI device performances by controlling the back gate voltages. So SOI performances will be much optimistic with proper control of the back-gate voltage for the already- proven- high- performance (APHP) SOI VLSIs.
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We previously developed and presented the 3D ion implantation simulation code, TRICSI. In this paper, we performed the multiple implants into (100) silicon substrate with our recently enhanced version. Our results for the multiple implants were compared with the previously published SIMS data and obtained the good agreements. In this paper the channeling behaviour of implanted impurity and the damage accumulation are analyzed and discussed in the simple 3D structure, named the Hole structure which has a rectangular implant window.
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This paper describes a performance degradation of static type input buffer due to the device degradation in menory devices using
$0.8\mu\textrm{m}$ CMOS process. experimental results shows that the degradation of MOS device affects the Trip Point shift in static type input buffer. We have performed the spice simulation and calculated the Trip Point with model parameter and measurement data so that how much the Trip Point(VLT) variate. -
The effects of denudation anneals on the properties of 256Mega-bit level devices were investigated. Based on the three-step anneal model, the redistribution of oxygen atom and the defect free zone depth were calculated. A significant outdiffusion of oxygen atoms is occurred during the denudation anneals at high temperature. Junction leakage current of P+/N-Well and N+/P-Well junctions, as a function of denudation anneal temperature, was decreased with increase of anneal temperature and is closely related with the behaviors of oxygen atoms. Also it is found that the denudation anneal at high temperature very effective for the fabrication of reliable 256Mega-bit level devices.
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The semiconductor technology for the deep submicron
$regime(0.18\mu\textrm{m})$ and larger wafer$diameters(300\mu\textrm{m})$ has been increased its cost with each wafer. Hence, in order to reduce the number of characterization experiments of a new process, lithographic modeling is more important than it was. In this paper, we introduced a new method to extract Dill ABC parameters from the refractive index changes. In order to evaluate our exact method, results of experiments and calculations for several resists were compared with other methods〔1〕through the lithographic simulation. -
In this paper, we analyzed electric field density and plasma condition to ICP reactor geometry structure, to generate plasma, to maintain plasma uniformity of large area LCD panel in ICP reactor also, we simulated electric field density for all kind existence current (antena and plasma current) in ICP reactor to analyze plasma antena structure
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This paper presents the characteristics of each MOS device and Bipolar device, then investigates about how these devices take effect on BiCMOS inverter from 300K to 470K. The turn-off and Logic swing characteristics of BiCMOS inverter are degraded by the electrical characteristics of the MOS to around 400K, but over that temperature enhanced by the characteristics of the Bipolar transistor.
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TiN thin films were grown on (100) Si substrate by atomic layer epitaxy at 130 -
$240^{\circ}C$ using TEMAT and NH3 as precursors. Reactants were injected into the reactor in sequence of TEMAT precursor vapor pulse, N2 purging gas pulse, NH3 gas pulse and N2 purging gas pulse so that gas-phase reactions could be removed. The films were characterized by means of x-ray diffraction(XRD), 4-point probe, atomic force microscopy(AFM) and auger electron spectroscopy(AES). -
We investigated the ultra-low energy B, P, and As ion implantation using ungraded MDRANGE code to form nanometer junction depths. Even at the ultra-low energies that were simulated in paper, it was found that channeling cases must be carefully considered. In the cases of B, channeling occurred above 500 eV, in the cases of P, channeling occurred above 1 keV, and in the cases of As, channeling occurred above 2 keV. Comparing 2D dopant profiles of 1 keV B, 2 keV P, and 5 keV As with tilts, we demonstrated that most channeling cases occurred not lateral directions but depth directions. Through thus results, even below 5 keV energy ion implant considered here, it is estimated that channeling effects are important in the formation of nanometer junction depths.
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The performance of inductively coupled plasma (ICP) is enhanced by axial magnetic field driven by alternating current Helmholtz coils in this work. Langmuir pobe is used to characterize the plasma, and the etching performance is demonstrated with phororesist stripping process. It is shown that its density and uniformity depends on the frequency of driving current to the magnetic field.
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Effects of current re-stress after anneal on leakage current and trapped charges in oxides are investigated. Current stress on 6 nm thick oxide has generated mostly positive traps within the oxide resulting in leakage currents. The interface states generated are several orders of magnitude smaller, determined by C-V and charge pumping method. Annealing has eliminated only the charged traps not the neutral traps, thus the leakage current and trap density are increased when the oxides are re-stressed.
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When a semiconductor(pMOSFET) sensor is exposed to ionizing radiation, electrons/holes are generated in its oxide layer. By the phenomenon of hole traps in oxide layer during their move, the characteristics of semiconductor is changed. This paper describes the output characteristic changes of two kind of pMOSFET(domestic, japan) after C0-60
${\gamma}$ -irradiation on them for their application as radiation accumulated dose monitoring sensors. We found the threshold voltage shifts (VT) of pMOSFETs in proportion to irradiated radiation dose and their linear properties. These results make us confirm that we will be able to develop good accumulated radiation dose monitoring sensors. -
NOX detecting gas sensors using TiO2 doped tungsten oxide semiconductor were prepared and their electrical and sensing characteristics have been investigated. In normal air condition, the sensors of WO3, TiO2 doped WO3 show grain boundary heights of 0.34 eV, 0.25 eV, respectively. The grain boundary barrier energy variation was increased by doping TiO2 into large variation of resistance to NOX gases. And doping the TiO2 4 wt.%, the particle size of WO3 polycrystal films showed higher sensitivity and better sorption characteristics to NOX gas than the pure WO3 films material in air at operating temperature of
$350^{\circ}C.$ The TiO2 doped WO3 semiconductor gas sensor shows nano-sized particle size and good sensitivity to sub-ppm concentration of NOX. -
In this paper, we have investigated the pyroelectric characteristics of the
$20\mu\textrm{m}-thick$ $LiTaO_3$ single crystal with black coating by using the nondestructive dynamic method. The$LiTaO_3shows$ the maximum pyroelectric coefficient (${\gamma}$ ) of$1.56 at 40Hz and the responsivity (Rv) is 488V/W at 2Hz. The noise equivalent power (NEP) is obtained as 3.95$\times$ 10-8C/\textrm{cm}^2K$$\times$ 10-10W/√Hz at 40Hz. The detectivity (D*) is obtained divided by the sample area and estimated to be 5.6$\times$ 108cm√Hz/W at 40Hz. These results, shows that the$LiTaO_3$ single crystals are the best candidates to pyroelectric IR sensors. -
Pyroelectric properties of rhombohedral
$Pb(ZrxTi_1-x)O_3ceramics$ with various Zr/Ti ratios of 84/16, 87/13, 90/10, and 93/7 are investigated using dynamic method. The response characteristics of PZT samples are examined by considering frequency dispersion. Since the reorientation of the grain does not the influence on the increase of frequency at low frequency (2~200Hz), the maximum pyroelectric response can be obtained with the change of spontaneous polarization. However, the pyroelectric response of PZT samples could be reduced as the spontaneous polarization decreases due to the restrain of the reorientation of the grain with the increasing of requency at high frequency (200~2000Hz). We have obtained the good pyroelectric response in the PZT sample having 84/16 Zr/Ti ratio, then the pyroelectric coefficient (${\gamma}$ ) and the figure of merit (FV) were$17.3nC/\textrm{cm}^2K$ and 2.28$\times$ 10-11Ccm/J, respectively. The noise equivalent power (NEP), the detectivity (D*) were 1.21$\times$ 10-7W/Hz$\frac{1}{2}$ and 8.26$\times$ 106cmHz$\frac{1}{2}$ /W, respectively. -
In this paper, a model of a Eddy-current probe coil with a ferrite core in the presence of a half-space with a layer is developed. The half-space with a layer is accounted for by computing the appropriate Green's function by using Bessel transforms. Upon introducing equivalent Amperian currents within a core to explain effect to a impedance change in the coil due to a (ferrite) core, we derive a volume integral equation, The integral equation is transformed via the method of moments into a vector-matrix equation, which is then solved using a linear equation solver. Through the above processing, we computed impedance value in a Eddy-current probe coil due to a conductivity change of layer.
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In this paper we realized non-contact sheet resistance measurement system using eddy current. Proposed system is designed to meet the requirements which is necessary when dealing with conducting thin films on large area LCD panel. With several metals we could get lift-off curves which has the same trend as in principal. Especially in the region of high conductivity this system has more discriminating ability than 4-point probe system.
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This paper presents a new configuration of dielectric bandpass filter using the comb-line filter design theory. This filter is composed of a homogeneous dielectric monoblock
$(\varepsilonr=35.5)$ with two metal post and a dielectric sheet$(\varepsilonr=9.8).$ In this structure, the RF leakage is suppressed without other shield housing. For the fabricated filter, insertion loss value in the passband region was 0.9dB(Max.) and return loss value was 19dB(Min). Also, this filter has a attenuation pole in the stopband. -
This paper presents the design method of a temperature stable stepped-impedance resonator using composite material. In this method temperature coefficient of dielectric constant
$(\tau\varepsilon)$ and thermal expansion coefficient$(\alpha1)$ of dielectric material were considered. Ba(Zn1/3Nb2/3)O3 and CaZrO3 as composite material having opposite signs of temperature coefficient of dielectric constant were selected. The length of this resonator for the temperature stability of resonance frequency was calculated at 900MHz, 1.4㎓ and 1.9㎓. It was found that the ratio of the length of positive$\tau\varepsilon$ materal to the length of negative$\tau\varepsilon$ material is constant at various resonance frequencies. -
This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6
$\Omega$ .cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0$\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches. -
In this study, power AlGaAs/InGaAs/GaAs PM-HEMT's for mm wave's were fabricated using Electron beam lithography and air-bridge techniques, and so on. DC and AC characteristics of the fabricated power PM-HEMTs were measured under the various bias conditions. For example, DC and RF characteristics such as S21 gain of 3.6 dB at 35 ㎓, current gain cut-off frequencies of 45 ㎓ and maximum oscillation frequencies of 100 ㎓ were carefully analyzed for design methodology of sub-mm wave power devices.
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A 35 ㎓ GaAs MMIC power amplifier was designed using a monolithic technology with AlGaAs/InGaAs/GaAs power PM-HEMTs, rectangualr spiral inductors and Si3N4 MIM capacitors. The GaAs power MESFETs in the input and output stages have total gate widths of 120 um and 320 um, respectively. Total S21 gain of 10.82dB and S11 of -16.26 dB were obtained from the designed MMIC power amplifier at 35 ㎓. And the chip size of the MMIC amplifier was 1.4
$\times$ 0.8$\textrm{mm}^2$ -
In this paper, wideband MMIC LNA's were designed using low Q matching network. gains of 23.6~25.4dB
$(24.5\pm0.9dB),$ noise figures of 0.9~2.8 dB were obtained from the designed wideband MMIC LNA in the frequency ranges of 1.2~2.8㎓. And, P1dB of 10.13 dBm, IP3 of 12.25 dB were obtained at the center frequency of 2 ㎓. A chip size of the designed wideband MMIC LNA is 1.4mm$\times$ 1.4mm. -
We used a three-dimensional inductance extraction program, Fasthenry for optimal design of the spiral inductors on silicon substrate. The inductance and quality factor of the spiral inductors with various design parameters were calculated so that the optimal parameter value was determined. The spiral inductors then were fabricated using different foundary processes and were measured using the network analyzer and microwave probes. The pad and other parasitics of measurement system were de-embedded using the y-parameter calibration technique. the inductors fabricated using the LG 0.8um process and HP 0.5um process showed the quality factor of 5.8 and 3, respectively. Finally the equivalent circuit farameters of the spiral inductors on silicon substrate were extracted from the measurement data using the matlab.
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본 논문에서는 MICROTEC〔3,4〕시뮬레이터를 이용하여 소트키 다이오드를 형성하고 금속-반도체 쇼트키 접촉에서 턴 온 전압과 항복 전압을 관찰하였다. 또한 여러 가지 쇼트키 장벽 높이를 가지는 금속을 사용하여 동일한 디바이스에서 이들 금속-반도체 접촉에 전압을 인가했을 때, 순 방향에서 턴 온 특성을 관찰하여 턴 온 전압과 역 방향에서의 항복 현상을 관찰하여 항복 전압을 확인하였다. 사용된 금속은 Au(0.8V), Mo(0.68V), Pt(0.9V), Ti(0.5V) 이며 반도체는 실리콘 n/n 구조가 형성되었다. 쇼트키 다이오드는 대 전력용 보다는 높은 속도의 스위칭 디바이스에 주로 응용되고 있으며 장벽의 높이가 높을수록 뚜렷한 정류 특성을 나타내어 순 방향 바이어스에서 빠른 턴 온 특성이 예상되는데 시뮬레이션 결과 또한 잘 일치하였다. 그리고 다이오드의 I-V 특성을 관찰하기 위해 역 방향 바이어스에서의 항복 전압을 관찰하였는데 쇼트키 장벽이 높을수록 낮은 항복 전압이 나타났다. 또한 디바이스 공정에서 epitaxial과 열처리 공정 후의 2차원적인 농도 분포를 나타내었다.
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CMOS Reference Voltage Generator(RVG) is designed to possible CMOS process without additional process steps. It is possible to compensate the temperature of RVG by using PTAT(proportional to the absolute temperature). Temperature compensation is profitable because
$\mun$ (electron mobility) is used. When VDD sweeps from 3V to 7V, variation ratio of Vref is 0.3125mV/V. Also temperature variation ratio of Vref is$047.1ppm/^{\circ}C$ during sweeping from$0^{\circ}C$ to$100^{\circ}C.$ Power Consumption is$50.3\muW.$ -
전자부품이나 설계된 회로시스템에 납땜을 하기 위해 인두를 사용하는데 누설전류, 서지전압, 정전기, 적절하지 못한 온도 등 여러 가지 악조건으로 인해 부품의 파괴를 가져온다. 특히 C-MOS로 설계된 소자의 경우는 다른 전자부품 보다 더 민감하기 때문에 파괴될 경우가 다발적으로 발생된다. 따라서 절연저항이 높고, 사용자가 적절한 온도로 제어할 수 있는 인두조절기 설계가 활발히 진행되고 있다. 본 논문에서는, 인두 히터에 센서를 삽입하여 이 저항의 변화율에 따라 온도를 감지하고, 주파수 방해를 최소화할 수 있는 Zero Voltage Switch IC를 사용하여 히터의 온도를 제어하였다. 또한, 사용자가 온도 변화를 알 수 있도록 A/D 변환기를 사용하여 시그먼트로 표시하였다. 기존에 설계된 시스템은 온도를 감지하는 센서가 민감하며 센서에서 감지된 신호가 비교기를 통해서 직접 히터의 온도를 제어하였기 때문에 온도 변화율이 매우 심하고, 이두팁이 분리되어있지 않기 때문에 절연저항이 매우 낮았다. 본 논문에서는, 이러한 문제점을 해결하기 위해 센서의 민감성을 최소화하고, Zero Voltage Switch IC를 사용하여 히터의 온도를 정밀하게 제어하였으며, 절연저항을 높이기 위해 인두팁의 중간에 세라믹을 삽입하여 팁에 온도만 전달될 수 있도록 용접을 하여 기존의 문제점을 개선하였다.
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A triangular/square waveforms generator with current controllable frequency is described. The genertor utilizes operational transconductance amplifiers as switching elements. The circuit built with commercially available components exhibits good linearity of current to frequency and relatively low temperature sensitivity.
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Novel bipolar transresistance amplifier(TRA) for high-accuracy current-mode signal processing is described. The TRA consists of two current follower for the current inputs, a current summer for curent-differential, and a voltage follower for the voltage output. The simulation results show that the impedence of the current input and the voltage output is 0.5
$\Omega$ and the 3-dB cutoff frequency when used as a current to voltage converter extends beyond 40 MHz. -
본 논문에서는 최근 급격히 수요가 증대하고 있는 휴대용 단말기의 수신기 선단에 사용되는 저잡음 증폭기(LNA)를 0.6㎛ CMOS공정 파라미터를 사용하여 설계하였다. 설계된 LNA는 전원 전압 ±1.2v, 900㎒대에서 동작하는 전류 재사용방식의 적층 CMOS구조로서 시뮬레이션 결과 전력소모가 9.45㎽, 전력이득은 23.7dB, 선형지수 OIP3는 7.6dBm을 나타내어 저전력 저잡음 특성을 얻었다. 사용된 인덕터의 Q는 3.5이다.
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In this paper, power amplifiers for PCS phone were designed with the GEC Marconi H40 HEMT libray. The 1st stage was carefully designed in order to obtain k〉1 using a parallel resistor, and its S21 gain of 18.3dB and input reflection coefficient of -4dB were obtained. And S21 gain of 18dB and input reflection coefficient of -7dB were obtained from the 2nd stage. Finally, total S21 gain of 38dB, input reflection coefficient of -16dB, power gain of 35.2dB, output power of 28.7dBm and PAE(power added efficiency) of 29% were obtained from the designed MMIC power amplifiers. The chip size is
$1.729 $\times$ 0.94\textrm{mm}^2.$ -
This paper presents the VLSI implementation of RS(reed-solomon) decoder using the Modified Euclidean Algorithm(hereafter MEA) for DVD(Digital Versatile Disc) and CD(Compact Disc). The decoder has a capability of correcting 8-error or 16-erasure for DVD and 2-error or 4-erasure for CD. The technique of polynomial evaluation is introduced to realize syndrome calculation and a polynomial expansion circuit is developed to calculate the Forney syndrome polynomial and the erasure locator polynomial. Due to the property of our system with buffer memory, the MEA architecture can have a recursive structure which the number of basic operating cells can be reduced to one. We also proposed five criteria to determine an uncorrectable codeword in using the MEA. The overall architecture is a simple and regular and has a 4-stage pipelined structure.
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This paper introduces a sigma-delta DAC with a fully-differential current-mode semidigital IFIR postfilter. A proposed fully-differential postfilter exhibits not only an improved SNR(signal-to-noise ratio) but also a reduced opwer dissipation.
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The full Viterbi detector for EPRML read channel system needs large area due to complex computation. There are several conventional methods to reduce the complexity such as GVA(Generalized Viterbi Algorithm) and BMS(Branch Metric Shift). This paper proposes another method, FVD(Folding Viterbi Detector), that has state transition diagram folded with inverted states. Compared with GVA detector, FVD requires only 61% gates and has lower power consumption and better BER performance.
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This paper describes a 6-b 400 MSPS CMOS folding and interpolating(F&I) ADC. To overcome the delay difference of an MSB part and an LSB part in a typical F&I ADC the ADC is composed of only one LSB part and to alleviate the offset voltage of comparators in the LSB part preamplifiers are used in front of the comparators. This paper analyzes a folder and presents a design procedure of the folder. The ADC has the DNL of 0.3 LSB and the INL of 0.6 LSB and consumes the power of 120mW
$$ 3 V. The ADC is designed in a 0.6$\mu\textrm{m}$ CMOS process. -
Today SOC(system on a chip) is a trend in VLSI design society. Especially MML(merged memory Logic) process provides designers with good chances to implement SOC which is consists of DRAM, SRAM, Logic and A/D mixed mode ciruit blocks. Designers need good circuit library which is reliable and easy to tune for specific design. For this need we present semi-automated analog compiler methodology. And we aplied this design methodology to resistor-string DAC design.
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This paper presents a 500MHz 1.1㎱ 32kb synchronous CMOS SRAM macro using
$0.35\mu\textrm{m}$ CMOS technology. In order to operate at high frequency and reduce power dissipation, the designed SRAM macro is realized with optimized decoder, multi-point sense amplifier(MPSA), selective precharge scheme and etc. Optimized decorder and MPSA respectively reduce 50% and 40% of delay time. Also, a selective precharge scheme reduces 80% of power dissipation in that part. -
This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.
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This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a
$0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is$20\muV/^{\circ}C,$ supply voltage dependency is$\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is$5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC. -
본 논문에서는 wide data-width DRAM을 위한 flexible column redundancy scheme을 제안하였다. 구현된 redundancy scheme은 DB line shift method를 사용하여 wide data-width를 갖는 고집적 DRAM에 적용할 때 기존 redundancy scheme보다 더 작은 redundancy cell 면적과 fuse개수를 가지면서 더 큰 flexibility를 가지게 되었다.
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본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.
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Fault simulation for large and complex sequential circuits is highly cpu-intensive task in the intergrated circuit design process. In this paper, we propose CM-SIM, a concurrent fault simulator which employs an optimal memory management strategy and simple list operations. CM-SIM removes inefficiencies and uses new dynamic memory management strategies, using contiguous array memory. Consequently, we got improved performance and reduced memory usage in concurrent fault simulation.
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Fault dropping is a very important part of test generation process. It is used to reduce test generation time. Test generation systems use fault simulation for the purpose of fault dropping by identifying detectable faults with generated test patterns. Two kinds of delay fault model is used in practice, path delay fault model and gate delay fault model. In this paper we propose an efficient method for gate delay test generation which shares second test vector.
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In this paper, we propose an implementation of an efficient parallel Radon transform on TMS320C80-based system. For an N
$\times$ N SAR image, we can obtain O(NM/p) of the conventional parallel Radon transform, by representing the projection patterns in Radon space variables instead of the image space variables, and pipelining the algorithm, where p is the number of processors and M is the number of projection angles. Also, we can reduce the time for the dynamic load distribution among the nodes and the communication overheads of accessing the global memories, by pipelining the memory and processing operations by using tripple buffer structure. Experimental results show an efficient parallel Radon transform of speedup Sp=3.9 and efficiency E=97.5% for 256$\times$ 256 image, when implemented on TMS320C80 composed of four parallel slave processors with three memory blocks. -
A scalable parallel algorithm is proposed for efficient image component labeling with local operatos on a mesh connected SIMD computer. In contrast to the conventional parallel labeling algorithms, where a single pixel is assigned to each PE, the algorithm presented here is scalable and can assign m
$\times$ m pixel set to each PE according to the input image size. The assigned pixel set is converted to a single pixel that has representative value, and the amount of the required memory and processing time can be highly reduced. For N$\times$ N image, if m$\times$ m pixel set is assigned to each PE of P$\times$ P mesh, where P=N/m, the time complexity due to the communication of each PE and the computation complexity are reduced to O(PlogP) bit operations and O(P) bit operations, respectively, which is 1/m of each of the conventional method. This method also diminishes the amount of memory in each PE to O(P), and can decrease the number of PE to O(P2) =Θ(N2/m2) as compared to O(N2) of conventional method. Because the proposed parallel labeling algorithm is scalable, we can adapt to the increase of image size without the hardware change of the given mesh connected SIMD computer. -
To develop an effective virtual prototyping methodology for the PLC(Programmable Logic Controller) based real-time systems, a conversion algorithm from RLL(Relay Ladder Logic) to statechart is presented in this paper. The RLL is the main programming language to represent the operation of the PLC, and the statechart is the most widely used tool in the field of virtual prototyping in order to represent the behaviour of real-time systems. A virtual prototyping for an example case is implemened to evaluate the benefit of the proposed algorithm.
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실시간 동영상의 전송을 위해 본 논문에서는 USB를 전송매체로 하여 구현했다. USB는 키보드, 스태너, 모뎀등 다양하게 사용되고 있는 인터페이스를 한나로 통일하고, 포트의 부족을 해결하기 위해서 개발된 것으로 고속의 데어터전송(12Mbps)을 가능하다. USB의 고속데이터 전송의 특징은 정지화상(JPEG) 뿐만 아니라 실시간 동영상(MPEG1, MPEG2)의 전송을 가능하게 한다. 본 논문에서는 USB로 실시간 동영상 전송을 위한 시스템 구조를 제시하였고 보다 효율적인 데이터 전송을 위한 USB Data Transfer Type에 관해 연구하였다. 720×480의 동영상의 압축을 위해 기존의 널리 이용되는 DCT대신 wevelet 알고리즘을 이용하였고 실시간 압축과 복원을 위해 video compression codec인 adv601를 사용하여 동영상 및 정지화상압축을 하였다. 또한 DSP(TMS320C32)를 이용하여 Quantization Bin Width Calculation을 함으로써 video bit stream의 크기를 가변적으로 제어하려 하였다. 이로서 동영상의 전송시 발생될 수 있는 데이터 병목현상을 해결 하였고 USB뿐만 아니라 다양한 통신망{ISDN(128Kbps), T1(1.5Mbps) T3(45Mbps)}에서의 동영상의 실시간 전송이 가능한 시스템 구조를 제시하였다.
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In this paper, we developed an outdoor augmented reality system which has remote real scences acquisition ability. The real scenes acquisition system consists of image acquisition system, tracking system, wireless data transceiver and power supply. Tracking system that consists of Tans Vector and RT-20 measures a position and attitude of the CCD camera that attached at the remote control helicopter. Wireless data transceiver system is utilized for data transmission of remote system that of attitude, position information, andreal scenes data that acquired by the CCD camera. Maximum propelling power of remote control helicopter is 15Kg, so we used 7.2V li-ion cell as a power supply for system minimize. As the results of experiment, the developing system presented application possibility of remote information acquisition system such as construction simulation & estimation, broadcasting, tour guide.
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This paper deals with the vehicle arbitration algorithm used in communication system between vehicles and a roadside control unit. To Improve the performance of vehicle arbitration, a random delay counter method is taken into account and modified to select the optimal maximum count value according to the vehicle arrival rate. The suggested algorithm is tested by computer simulation andthe enhanced performance was shown. This method could be applied to various systems which include the communications between transponders and a control unit.
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This research aims at developing a single chip multiprocessor for high-performance computer system. Our design approach is to design a relatively small and simple processor unit and to integrate multiple copies of the unit in an efficient way. The proposed multiprocessor is composed of four CPUs and one graphic coprocessor. The four CPUs share the graphic coprocessor and each CPU implements the 64-bit SPARC-V9 instruction set architecture. This paper gives an overview of the proposed microarchitecture and discusses the considerations made in the course of the design.
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As the performance of microprocessor improves, the design complexity grows exponentially. Therefor, it is very important to make the bug-free model as early as possible in a design life-cycle. This paper describes the simulation-based functional verification methodology for the RTL level description model. It is performed by multi-stage verification methods using extensive hand-generated self-checking tests supplemented with random tests. This approach is opplied to the functional verification of the GPU processor of Raptor and various bugs are detected.
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In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.
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This paper describes the microarchitecture of the integer processor unit of RAPTOR which is an on-chip multiprocessor. The integer processor unit implements the 64-bit SPARC-V9 architecture and supports by hardware out-of-order instruction execution. The unit is designed to be handy so that multiple copies of the unit cn be integrated with cache memories into a single chip. The design was proceeded in a top-down manner. The hardware description and its verfication were performed using Verilog-HDL.
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This paper introduces an instruction fetch unit which is designed for RAPTOR, an on-chip multiprocessor. In order to reduce control hazards, the proposed fetch unit supports a hybrid branch prediction scheme which consists of a static scheme and the 2bC branch prediction scheme. The fetch unit also utilizes the branch folding technique with two instruction buffers to avoid the branch penalty caused by imspredictions. Instructions are predecoded in the fetch unit to achieve extra performance gain.
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In this paper proposes a new bit-parallel structure for a multiplier over GF((Pn)m), with k-nm. Mastrovito Multiplier, Karatsuba-ofman algorithm are applied to the multiplication of polynomials over GF(2n). This operation has a complexity of order O(k log p3) under certain constrains regardig k. A complete set of primitive field polynomials for composite fields is provided which perform modulo reduction with low complexity. As a result, multiplier for fields GF(Pk) with low gate counts and low delays are constructed. The architectures are highly modular and thus well suited for VLSI implementation.
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근래에 들어 컴퓨터 기술은 멀티미디어 기수의 발달과 더불어 그에 따른 데이터량의 증가로 인해 데이터를 처리, 전송, 저장하는 모든 부문에서의 고속, 대용량화를 요구하고 있다. 이 중에서 특히 저장장치 부문은 응용 프로그램이 대형화되고 멀티미디어화에 따른 데이터량이 크게 증가하는 추세에 있기 때문에 지속적인 용량 증가가 요구되고 있다. 이런 상황에서 주목을 받고 있는 것이 신호처리 방식을 개선하여 저장장치의 기록 밀도를 향상시키는 기술의 하나인 partial response maximum likelihood (PRML) 기술이다. PRML 방식은 HDD 나 광 디스크로부터 데이터를 읽어낼때의 신호처리 기술 중의 ㅎ나로 신호간 간섭을 허용하여 데이터 속도를 증가시키고, 신호를 재생할 때 신호간 간섭을 보상하여 원래 신호를 복원해 내는 기술이다. 이를 이용하면 기존의 기록방식에 비해 기록밀도를 20-50% 정도 높일 수 있다.〔1〕〔2〕
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This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.
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We designed a 3.3 V, 400 Mbps IEEE-1394 physical layer transeiver on 0.6um 1P3M CMOS process. The transceiver drives a twisted pair cable of which differential impedance is 110
$\Omega$ so that differential amplitude reaches 200 mV at 400 Mbps and restores this small signal to rail-to-rail. Also, the transceiver arbitrates the interface among nodes on a bus configuration and supports both synchronous interface and asynchronous interface. -
In this paper, we presents a method for multi-level logic mainmization which is suitable for the minimization of look-up table type FPGAs. A pattern extraction algorithm is minimized AND/XOR multi-level circuits. The circuits apply to Roth-Karp decomposition which is most commonly used technique in the FPGA technology mapping. We tested the FPGA synthesis method using pattern extraction on a set of benchmark. The proposed method achieved reductions on the number of LUTs in mapping soultion as compared with MISII(or SIS) or previous results〔5〕
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This paper presents a constant gm input stagefor low-voltage rail-to-rail operational amplifier. A proposed scheme uses two current paths to keep sum of the biasing currents of the complimentary input pairs. The op amp was designed in a
$0.8\mu\textrm{m},$ n-well CMOS, double-polysilicon and double-metal technology. This achieved in weak inversion. The circuit can operate in power supply voltage from 1.5V up to 3V. An open-loop gain, AV, was simulated as 84dB for 15pF load. An unit-gain frequency, fT was 10MHz. -
In this paper, a new class of bandpass filter using a modified Chebyshev lowpass filter function is described. The prosposed bandpass filter which exhibits diminishing ripples in the passband has maximum value at the center frequency. Due to the lower pole-Q, the performance in the frequency and time domains is improved as compared with the classical Chebyshev bandpass filter.
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As we know, gigabit ethernet is a new technology to be substituted for current fast ethernet used widely in local area network. The switch used in gigabit ethernet should deal with frames in giga-bps. To do such a fast switching, we need that serveral processes meet the budgets, such as MAC address table lookup, several giga speed path setup, fast scheduling, and etc. Especially MAC address table lookup has to be processed in the same speed with speed of incoming packets, thus the bottleneck in the process can cause packet loss by the overflow in the input buffer. We devise new practical hardware hashing method to perform fast table lookup by minimizing the number of external memory access and accelerating with hardware.
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A novel bipolar circuit technique for realizing linear transconductor is described. The proposed circuit has superior linearity and temperature characteristics when compared with the conventional transconductor. The theory of operation is presented and computer simulation results are used to verify theoretical predections. The simulation results show close agreement between predicted behaviours and experimental performances.
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This paper propose the method to produce GRM(Generalized Reed-Muller)expansion. The general method to obtain GRM expansion coefficient for p valued n variable is derivation of single variable transform matrix and expand it n times using Kronecker product. In this case the size of matrix increases depending on the augmentation of variables. In this paper we propose the simple algorithm to produce GRM coefficient using a single variable transform matrix.
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This paper proposes a constant time-delay filter with low sensitivity, which can be used for hard-disk drive. The sensitivity of 2nd order lowpass filter by two kinds of method, one is based on lossy integrators and the other is lossy and lossless integrators is analyzed and designed. SPICE simulation shows fesibility of a filter by the proposed approach.
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The Insulated Gate Bipolar Transistor has the characteristics of MOSFET and BJT. The characteristics of proposed device exhibit high speed switching, the voltage controlled property, and the low ON resistance. This hybrid device has been used and developed continuously in the power electronic engineering field. We can simulate many IGBT circuits, such as the motor drive circuit, the switching circuits etc, with PSpice. However, some problems in PSpice is that the IGBT is old-fashioned and is very difficult to get it. In this paper, the IGBT in PSpice is considered as the basic structure. We changed the valuse of base width, gate-drain overlaping area, device area, and doping concentration, then calculated MOS transconductance, ambipolar recombination lifetime etc. Using this resultant parameter, we could predict the transient response characteristicsof IGBT, for examplex, voltage overshoot, the rising curve of voltage, and the falling curve of current.
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A new active power filter (APF) circuit with a current compesation estimation method is proposed. The current compensation estimation method replaces a current sensor with an estimating circuit and therefore reduces the implementation cost In addition, a simple control scheme, based on the energy balance concept, is adopted to control the voltage of a DC capacitor. Therefore energy change in the DC capacitor can be compensanted in the next cycle. Since a sampling technique is used, a larger DC capacitor voltage ripple can be permissible and a relatively smaller DC capacitor can be used. The proposed method has advantages of the reduction of one current sensor, low implementation cost, and fast transient responses. The theoretical analysis and simulation results are given. The proposed control method is successfully verified by computer simulation.
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경혈을 대상으로 인체를 진단하는 의료기기들은 경혈점에 미세한 직류전류를 인가하고, 이 점에서의 전기저항과 세포의 분극에 의해 반응하는 경락체계의 균형상태를 측정하여 인체를 종합적으로 진단한다. 따라서 전 과정이 정확한 경혈의 위치에서 이루어져야만 치료효과와 진단의 신뢰성이 보장된다. 그러나 대부분의 경락관련 치료기들이 정확한 혈위식별에 어려움이 있고 사용자의 전문적 숙련을 요구한다. 따라서 선행연구에서 일정한 주파수로 교호되는 자극패턴(SPAC) 방식을 사용하여 식별률을 높인 혈위식별기 DM96A-1를 개발하였다. DM96A-1은 단일전원이 양방향으로 교호되는 전류로 자극펄스를 출력하고 측정범위가 0.5∼50㎂인 전류메터와 레벨메터를 이용하여 혈위의 전류량을 표시한다. 이에 따라 방향전환 소자의 두 채널 제어신호가 교호되는 과도기에서 두 자극패턴의 중첩 도통에 의해서 누설전류가 발생하는 경우가 있으며 이를 제거하기 위하여 정밀한 조정을 필요로 하는 불편이 있었다. 따라서 이와 같은 단점들을 보완하여 신뢰성 있는 출력 파라메터를 얻을 수 있도록 마이크로프로세서 i80c196kc를 사용하여 DM96A-2를 재 설계하였으며 임상실험에 의하여 개선된 최적 파라메터의 타당성을 검증하였다.
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본 연구에서 시각 장애인을 위한 인터넷 웹 브라우저를 개발하였다. 인터넷 웹 브라우저 시스템은 인터넷에 연결된 컴퓨터와 문자 출력을 위한 점자 출력기와 음성 합성기, 그림 이미지의 출력을 위한 촉감 출력기, 인터넷 웹 페이지를 출력하기 위한 점자 프린터로 구성된다. 인터넷의 문자 정보는 점자로 변환하여 점자 출력기로 출력하였고, 전자석(solenoid) 방식의 구동기로 동작하는 촉감장치로 인터넷의 그림 정보를 출력하였다. 본 시스템을 이용하여 시각 장애인은 인터넷 웹 사이트 정보를 접근할 수있다.
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The propose of this paper is to implement the master slave control with non-actuated Master Arm scheme by using spaceball. The spaceball is a device which can receive all 6-DOF at once and was selected because it isn't dependent to robot type or it's DOF but can be used to produce information about 3D coordiante system The proposed method's main benefit is that one who has no idea about robot structure can control the manipulator with easy. The simulation is supported with 3 modes of control to accomodate unexpected situation. The proposed implementation has probed that a non-trained user can manipulate the slave with intuition without much difficults.
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In this paper, we designed the computer input device for rehabilitation of people with hand disabilities. This input device is made up of two Gyrostar sensors attached in the orthnormal directions of x, y axes. Gyrostar is a sensor for angular Acceleration. This device is attached by the user's head side. Head movement is detected by analysing and processing the output wave signals from the sensors therefore enabling the user to move the mouse pointer that helps to operate the computer. This method does not necessitate a complex hardware or a long installation process, which was formerly the case, and uses real time algorithms which enables simple emulation of a computer mouse. The interface of this device and the mouse are the same.
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Korean Text to Sign Language Traslator could be applied to learn letters for both the deaf and hard-of-hearing people, and to have a conversation with normal people. This paper describes some useful dictionaries for developing korean text to sign language translator; Base sign language dictionary, Compound sign language dictionary, and Resemble sign language dictionary. As korean sign language is composed entirely of about 6,000 words, the additional dictionaries are required for matching them to korean written language. We design base sign language dictionary which was composed of basic symbols and moving picture of korean sign language, and propose the definition of compound isng language dictionary which was composed of symbols of base sing language. In addition, resemble sign language dictionary offer sign symbols and letters which is used same meaning in conversation. By using these methods, we could search quickly sign language during korean text to sign language translating process, and save storage space. We could also solve the lack of sign language words by using them, which are appeared on translating process.
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An adaptive block DCT coding scheme is implemented with the same average distortion designated for each block. In this paper, a new implementation of the Discrete Cosine Tranform(DCT) for image is described. Practical system application is attained by maintaining a balance between complexity of implementation and performance. ADCT sub-blocks are sorted into mean according to level of image activity, measured by mean within each sub-block. Excellent performance is demonstrated in terms of PSNR of original and reconstructed images.
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Recently efficient image coding algorithms using zerotree have been proposed. In these methods, the locations of nonzero wavelet coefficients are encoded with a tree structure, called zerotree, which can exploit the self-similarity of the wavelet pyramid decomposition across different scales. These are very effective, especially in low bit rate image coding. In this paper, two zerotree image coding algorithms, EZW and SPIHT, are briefly introduced, and a new zerotree searching scheme is proposed to emphasize the significance of a wavelet coefficient by its orientations as well as its scale.
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Nowadays it is possible to make realization of Multimedia service by virtue of developing computer hardware technique and high-bandwidth network. But Multimedia service has some problems. Its file need large storage. Above all, Analog CCTV used in recent has been utilized for various purpose in ban, company and public institution, but this has many defects such as management, low resolution, and etc. To overcome this problems, multimedia component-file-have to be reduced in size. This paper proposes adaptive MPEG-1 video to reduce file size. The method in this paper is realized that according to movement variation, file size is reduced by adaptively making use of MQuant.
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Many playback methods of MPEG-1 video were developed and are have beendeveloped now. But nomal playback method demands great time. In this paper we designed and implemented the scene transition playback method of the MPEG-1 video data. The previous studies of scene transition playback have used to the DC or edge information after decoding process of picture. In this paper, scene transition is detected by macroblock information from MPEG-1 compressed area, then decodes and playbacks the only scene transition picture. This MPEG-1 video player was implemented by decoding control. So it is possible to add special playback method to MPEG-1 video player. As the result, which is proposed in this paper the scene transition method can minimize to decoding calculation and decrease to playback time of the MPEG-1 video data.
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In this paper, we proposes Moving Picture Compression reducing bit numbers within the block by probability in 3D-DCT considered of temporal axis. From Delta Modification theory for frequency components, bit numbers within the block(4
$\times$ 4) were properly compressed by using the Probability Entropy. At the result for the proposed algorithm, we could find that the values of PSNR for resolution and the compression rate were better than existing methods. -
Video data is usually stored in a compressed format in order to reduce the storage space. For efficient browsing, searching, and retrieval of compressed video sequences, size-reduced images (or DC images which are formed with block DC coefficients) are generally preferred to avoid unnecessary computational complexity. In this paper, we propose a DC image extraction scheme appropriate for scene analysis and efficient browsing of compressed video sequences. The proposed algorithm utilizes predicted low frequency AC coefficients to achieve better approximation and to reduce the error drift. Due to the AC prediction based on a quadratic surface model, the proposed scheme requires no additional memory compared with the previous zero-order or first-order approximation scheme. Simulation results show that the proposed scheme achieves better subjective and objective quality with minor additional operations.
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This paper presents a new morphological spatio-temporal segmentation algorithm. The algorithm incorporates intensity and motion information simultaneously, and uses morphological tools such as morphological filters and watershed algorithm. The procedure toward complete segmetnation consists of three steps: joint marker extraction, boundary decision, and motion-based region fusion. By incorporating spatial and temporal information simultaneously, we can obtain visually meaningful segmentation results. Simulation results demonstrates the efficiency of the proposed method.
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In this paper, an adaptive event detection algorithm is proposed, for which we use the statistics of subblock image and adaptive threshold levels. The adaptive threshold level for a parameter binarization is taken by averaging the corresponding paramerter obtained from several input images. As simulation results, it is shown that the proposed algorithm is much more adaptive to the input images and effective in event detection rate than the conventional difference based algorithms.
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현재 보안 시스템으로 가장 많이 쓰이고 있는 것 중에 하나가 여러 지역의 카메라로부터 영상 신호를 받아서 하나의 모니터에 여러 영상을 분할 해서 보여주는 시스템이다. 이 시스템의 기능 중에서 가장 중요한 것은 각 지역의 영상을 실시간으로 처리해줄 수 있어야 하는데, 이를 위해서는 영상 데이터를 놓치지 않고 모두 메모리에 저장할 수 있어야 한다. 본 논문에서는 4개의 영상을 하나의 화면으로 4분할 하여 출력하기 위한 시스템을 FPGA를 사용하여 구현했다. 일반적으로 화면 분할하는 시스템은 흑백의 영상만을 출력하는데, 컬러 영상 신호인 RGB 5:6:5모드의 데이터를 사용하여 컬러 영상을 그대로 화면 분할하여 출력하는 시스템을 구성했다. 또한, 화면을 나누기 위한 PIP(Picture In Picture) 등의 전용칩은 분할 화면의 수가 늘어날수록 그 시스템의 크기가 커지므로 순수하게 FPGA를 이용하여 로직을 설계해서 직접 필드 메모리 (FIFO)를 콘트롤 하도록 설계했다. 동기화 되어 있지 않은 메모리에 저장한 각 영상 데이터를 하나의 영상화면에 동기화시키기 위한 방법으로 일정한 타이밍마다 각 영상 데이터를 선택하는 선택 알고리즘(Choice Algorithm)을 제시하여 적용하였다. 선택 알고리즘에 따라서 동기화 되어 있지 않은 메모리에 저장한 각 영상 데이터를 하나의 영상화면에 동기화 시키기위한 방법을 로직으로 구현하여 적용한 시스템을 만들어서 직접 실험 및 테스트를 실행하였다. 로직을 구현하기 위해 사용한 FPGA(Xilinx 5200 Series)는 XC5210-5이고, 비디오 데이터를 저장하기 위한 필드 메모리(FIFO)는 μPD42280-30를 사용하였는데, 좀더 여유 있는 데이터 저장을 통해 선명한 화질을 얻기 위해서는 FPGA와 메모리를 더 빠른 타입으로 사용하는 것이 바람직하다. 내용 전개를 살펴보면 제 1절에서 본 시스템의 필요성 및 개발 동기, 개발 배경등에 대해서 간단히 설명하고 제 2절에서는 전체 시스템의 구조에 대해서 설명하고 제 3절에서는 본 시스템의 구조 중에서 가장 중요한 메모리 컨트롤에 대해서 간단히 설명하고, 제 4절에서는 시스템을 구현시켜 실험 및 결과에 대해서 분석한다. 마직막으로 결론 및 향후 계획에 대해서 기술한다.
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In order to detect the user's gaze position on a monitor by computer vision, the accurate estimations of 3D positions and 3D motion of facial features are required. In this paper, we apply a EKF(Extended Kalman Filter) to estimate 3D motion estimates and assumes that its motion is "smooth" in the sense of being represented as constant velocity translational and rotational model. Rotational motion is defined about the orgin of an face-centered coordinate system, while translational motion is defined about that of a camera centered coordinate system. For the experiments, we use the 3D facial motion data generated by computer simulation. Experiment results show that the simulation data andthe estimation results of EKF are similar.e similar.
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We present a novel multi-resolution block matching algorithm (BMA) for fast motion estimation. At the coarsest level, a full search BMA (FSBMA) is performed for searching complex or random motion. Concurrently, spatial correlation of motion vector (MV) field is used for searching continuous motion. Here we present an efficient method for searching full resolution MVs without MV decimation even at the coarsest leve. After the coarsest level search, two or three initial MV candidates are chosen for the next level. At the further levels, the MV candidates are refined within much smaller search areas. Simulation results show that in comparison with FSBMA, the proposed BMA achieves a speed-up factor over 710 with minor PSNR degradation of 0.2dB at most, under a normal MPEG2 coding environment. Furthermore, our scheme is also suitable for hardware implementation due to regular data-flow.
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This paper introduces an automatic face region extraction method. This method consists of two part: face recognition and extraction of facial organs which are eye, eyebrow, nose and mouth. In first stage, we use genetic algorithms(GAs) to get face region in complex background. In second stage, we use Geometrical Face Model to textract eye, eyebrow, nose and mouth. In both stage, stochastic component is used to deal with the problems caused by had lighting condition. According to this value, blurring number is determined. Average Computation time is less than 1 sec, and using this method we can extract facial feature efficiently from several images which has different lightning condition.
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In this paper, we propose an efficient marker extraction algorithm for initial image segmentation in a bottom-up segmentation scheme. The proposed algorithm generates dense markers in visually complex areas and coarse markers in visually uniform areas. which conforms to the human perceptual system. Experimental results show that the proposed method achieves better subjective quality for fine initial image segmentation.
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임상진단에 있어서 종종 문제가 되고 있는 호흡에 따른 두뇌부분의 가상적인 상하이동을 고려해서 위상 엔코드 축인 Y 방향만의 강체의 평행이동을 취급한다. 종래의 발견적인 축차 근사 반복처리에 의한 제거방법과는 달리, 본 연구에서는 MRI 촬상과정과 화상특성의 해석에 근거한 MRI 신호중의 체동성분과 화상성분을 단순한 대수연산에 의해 분리할 수 있는 새로운 구속조건을 도출한다. MRI 신호에 대해서 X 방향의 1차원 푸리에 변환을 행한 후의 Y 방향의 스펙트럼 위상값은 화상자신의 성분과 체동성분의 합이 되고 있다. 한편, 두뇌부위 등의 단층상에 있어서 주위의 피하지방 부분의 밀도는 거의 균일한 것 알려져 있어 이 부분위의 Y 방향의 1 라인 밀도분포를 대칭이라고 간주할 수 있다. 밀도함수가 대칭인 경우 스펙트럼의 위상은 그 위치에 대하여 선형적으로 변화한다. 따라서 이 선형함수로부터 벗어난 성분을 체동성분으로 분리할 수 있다. 이러한 구속조건에 기초를 둔 근거가 명확한 아티팩트의 제거방법을 제안한다. 아울러 본 방법의 유효성을 확인하기 위해 호흡에 의한 주기성의 체동을 가진 MRI 화상에 대해서 시뮬레이션을 행하였다.
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We propose a new method for merging partical regions which have similar motion characteristics. In the proposed method, the trajectories of each partial regions are computed and the regions consisting a same object are merged by a similarity function defined in this paper. The similarity function is defined to take into consideration the motion characteristics of the trajectories. The proposed method shows good performance when the regions of an object show little variation in size and shape.
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In this paper, we present a comparative performance analysis of several blocking artifact reduction algorithms. For the performance analysis, we propose a block boundary region classification algorithm which classifies each horizontal and vertical block boundary into four regions using brightness change near the block boundary. The PSNR performance of each algorithm is compared. The MSE according to each block boundary region is also compared. Experimental results show that the wavelet transform based blocking artifact reduction algorithms have better performance over the other methods.
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In this paper, the importance of including small image features at the initial levels of a progressive second generation video coding scheme is presented. It is shown that a number of meaningful small features called details shouuld be coded in order to match their perceptual significance to the human visual system. We propose a method for extracting, perceptually selecting and coding of visual details in a video sequence using morphological laplacian operator and modified post-it transform is very efficient for improving quality of the reconstructed images.
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Region based coding consistsof image segmentation contour and texture coding. Contour coding techniques can be classified into contour or shape-oriented approaches. In this paper, geodesic skeleton based on shape-oriented approach is used for contour coding. Efficient application of geodesic skeleton for contour coding based on the characteristics of regions in segmented image will be discussed.
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A content-base search method is required for video which has an unformatted and huge size of data. The index techniue is necessary for the content-based search of the video data. The first step of the video indexing is a cut detection. We propose a dynamic threshold method which change a threshold value during the cut detection process. We demonstrate that the proposed method is more efficient than the existing methods.
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비디오 스트림과 오디오 스트림 그리고 제어신호등의 서로 다른 종류의 digital data 들을 저장 또는 전송하기 위해서는 하나의 스트림으ㅗ 통합하기 위해 다중화 과정을 거쳐야 한다. 이러한 다중화 과정에서 가장 중요한 문제점은 하나로 묶여진 일련의 스트림을 원래의 순차대로 복원해주는 동기화 문제이고, DVD-Video에서는 MPEG2 system를 이용한 동기방식을 사용한다. 본 논문은 DVD 규격에 맞추어 Microsoft의 Visual C++5.0을 이용하여 software로 VOB를 구현하였다. 입력 스트림은 MPEG2로 압축된 비디오스트림과 최대 8개의 5.1채널 AC3 오디오스트림이고 각 스트림은 frame단위로 구성이 된다. 이 frame들을 단위로 time stamp가 부여되며 time stamp의 비교에 의해 우선 순위를 부여하여 encoding을 하게된다. 그리고 같은 time stamp를 가졌을 경우 발생하는 encoding 순서의 문제는 스트림별로 미리 우선 순위를정함으로써 해결했다.
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This paper presents a new method for reconstructing 3 dimensional object model using a zoom camera. The proposed method uses zoom images to find the distance(D) between camera and object. Also the method uses images obtained around the object to find an
$angle(\theta)$ between two connected planes of the object. With the D and$\theta,$ we can reconstruct the real sized 3-D model of object with less errors without stereo camera or rangefinder. -
We have implemented a sign language animation system using 2D and 3D models. From the previous studies, we find out that both models have several limitations based on the linear interpolation and fixed number of frames, and they result in incorrectness of actions and unnatural movements. To solve the problems, in this paper, we propose a sign language animation system using spline interpolation method and variable number of frames. Experimental results show that the proposed method could generate animation more correctly and rapidly than previous methods.
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In this paper, we propose a new auto focus algorithm using variance which estimate spread characteristic of image. In the proposed algorithm, the focus value is calculated via variance of difference between two adjacent pixels. This algorithm, we propose, show much more sharp focus curve than any other algorithms. It is shown experimentally that the proposed auto focus algorithm can be a efficient alternative to existing Tenengrad-based auto focusing algorithms.
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본 논문에서는 랜덤 시퀀스와 직교코드를 이용하여 비화성이 강한 디지털 정보은폐 방법을 제시하였다.
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In this paper, we applied FFT to PCB Images, cutting unnecessary singals and noise, moving the starting point to center of image and used rotaion transform. from the detected edge Hough Transform identify the length, but not the angle, so we matched PCB images with using rotation transform to identify length and angle. After rotation transform we employ Least Squared Method to exact stereo matching.
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Geological structures such as fault and fracture patterns provide important information about preliminary exploration of mineralized areas and geological characterization. We apply a filtering method taking the sun's azimuth angle into account to a shaded relief image derived from a digital elevation model (DEM), by which even linear edges extending parallel to the sun direction can be effectively extracted. Then, Generalized Hough tranform is applied to extract lineanments which correspond to fault and fracture patterns.
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This paper describes the implementation of the machine vision system and the method of classifying the objects. Its system described in this paper is consisted of robot, conveyer system, warehouse, and machine vision. This system first recognizes the object on conveyer, and then robot moves it to the warehouse. The position of the object on conveyer is always not constant, because it is not easy to extract the feature of its object and classify it into one of several categories. In this paper, to classify or inspect the pattern of the object, we propose the method of template matching using feature vector such as position invariant moment and mophological operation such as opening and closing. And we indentified an unregistered object using unsuperviser learning method and assigned it to the new pattern. We implemented its system and obtained satisfied results.
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This paper describes the algorithm which extracts moving vehicles from sequential images and tracks those vehicles using Kalman filter. This work is composed of a motion segmentation stage which extracts moving objects from sequential images and gets features of objects, and a motion estimation stage which estimates the position and the motion of moving objects using Kalman filter. In the motion estimation stage, applying to affine motion model we divided the Kalman filter into position filter and velocity filter to employ linear Kalman filter. Multi-target tracking requires a data association component that decides which measurement to use for updating the state of which object. We use pattern recognition method to solve this problem.
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In this paper, we propose an efficient vehicle detection and classification algorithm for an electronic toll collection, which is based on shadow robust vehicle presence test. In order to improve the performance of vehicle presence test, we use correlation coefficients between wavelet transformed input and reference images, which takes advanage of textural similarity. We compare the performance of the vehicle presence test with those of some conventional approaches that use variance of frame difference. Experimental results from field test show that the proposed vehicl detection and classification algorithm performs well even under abrupt intensity change due to the characteristics of sensor and occurrence of shadow.
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In this paper, a fingerprint classification algorithm is presented. Fingerprint types are classified into five categories: arch, tented arch, left loop, right loop and whorl. Singular points (cores and deltas) are detected using Poincare index on the directional image smoothed by adaptive window size. The method is shown to be robust to the variation of fingerprint image qualaity.
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본 논문에서는 스캔 영상의 외곽선을 추출하기 위해, 경계선 검출값들의 공간적 특성을 이용하여, 경계선 검출 값들을 계산하였다. 그리고 경계선 검출 값들의 편차 정도에 따라 임계값을 결정 한 다음 스캔 영상의 외곽선을 추출하는 방법을 제시하였다.
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스테레오 물체추적 시스템은 스테레오 비젼 시스템의 입체 영상에서 나타나는 스테레오 시차를 없애 주는 주시각 제어와 이동 물체를 영상의 중앙에 위치시키기 위한 팬/틸트 제어를 통해 이동 물체를 추적하게 된다. 본 논문에서는 스테레오 물체추적 시스템의 새로운 접근방법으로 적응적 물체 추적이 가능한 광 JTC를 이용해 이동 물체를 추적하는 스테레오 물체추적 시뮬레이터를 구현하였다. 이를 이용하여 여러 종류의 입력 영상에 따른 광 JTC 의 추적 결과를 분석하여 실험 결과를 예측할 수 있었으며, 이를 광학적으로 구현할 경우 배경 잡음에 강하고 실 시간적 물체 추적이 가능한 스테레오 물체추적 시스템을 구현할 수 있음을 제시하였다.
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A real-time holography system using LCD with CCD camera is proposed. In this system, the rainbow hologram is used since it can be reconstructed by white light source. And to record on CCD camera, a kind of in-line holography method is used to widen the width of the fringe pattern. The interference fringe pattern by proposed system is detected with CCD camera and transferred to the LCD A 3-dimensional image is reconstructed when a white light source illuminates the LCD. So it can represent 3 dimensional moving images at real-time. In this paper, to confirm the usefulness of the proposed method, the reconstructed image by holographic film is compared to the same reconstruct image by LCD. In the recording of the interferenced processing, the optimal ratio of the reference and object beam intenstiy is also investigated.
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We fabricated sampled fiber grating by double-exposure method. First, a short-period grating was written into the hydrogen-loaded single mode fiber and then the refractive index was modulated over it by an amplitude mask. It was observed that several transmission dips appear due to the index modulation. The thermal and strain responses were measured over
$40-180^{\circ}C$ and$0-1800\mu\varepsilon,$ respectively. The dips have the same and linear sensitivity to both physical quantities over the range of measurement. -
Inthis paper, we design 4
$\times$ 4 optical star coupler with tapered coupling structure. The 4$\times$ 4 optical star coupler consists of four 3dB couplers and a 100% coupler with tapered structure. This star coupler is designed by the 2 dimension FD-BPM(finite difference beam propagation method) using TBC(transparent boundary condition). consequently, the maximum power unbalance ratios of relative output power from each of the output waveguides for each of input guides are less than 0.1dB, and the transmission efficiency is more than 99%. -
An optical adder for a modified signed-digit(MSD) number system using joint spatial encoding method is proposed. In order to minimize the numbers of symbolic substitution rules, nine input patterns were divided into five groups of the same addition results. For recognizing the input reference patterns, masks and reference patterns without any other spatial operations are used. This adder is implemented by smaller system in size than a conventional adder.
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We demonstrate wavelength conversion of 2.5 Gb/s optical signals by cross-gain modulation (XGM) in a semiconductor optical amplifier (SOA). We investigate the effect of input pump and probe powers on the extinction ratio and power penalty to be a measure of performance in wavelength converters. As a result, we show that the best bit error rate (BER) performance can be obtained when the probe power is kept 3 dB weaker than the pump power. And we investigate the effect of wavelength detuning on performance in wavelength converters.
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The experimental optical cross-connect based on delivery and coupling switch features all-optical property. It consists of erbium-doped fiber amplifiers, arrayedwaveguide gratings, optical switches and optical combiners. In 4 channel wavelength division multiplexing with 1.6 nm spacing, the difference in power level among channels for output signals from the optical cross-connect was within 2 dB.
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In this paper, we present a gridless router for MCMs. Instead of the commonly employed grid a set of comer stitched tiles are used as a routing framework. The router routes variablewidth pins with wires of any width. It also a allows arbitrary location of terminals, wires, and vias. It performs faster than most grid-based MCM routers and produces the routing results which are comparable to their achievements.
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IC testing plays a very important role in IC manufacturing process. Modern complex ASIC chips making it difficult for gate level and RLT level test generation techniques to generate good test vector in resonable time. In this paper we proposed new test pattern generation method in VHDL description to detect manufacturing faults. This method based on software testing can easily generate test vector and independent to synthesis result.
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An efficient algorithm for clock skew optimization is proposed in this paper. It construct a new clock routing topology which is the generalized graph model while previous methods uses tree-structured routing topology. Edge-insertion technique is used in order to reduce the clock skew. A link-edge is inserted repeatedly between two sinks whose delay difference is large and the distance is small. As a result, the delay of a sink which has the longer delay is decreased and the clock skew is reduced. The proposed algorithm is implemented in C programming language. From the experimental results, we can get the total wire length minimization under the given skew bound.
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A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.
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We propose an algorithm which processes the floating-point
$n_{addition}$ traction and rounding in parallel. It also processes multiplication and rounding in the same way. The hardware model is presented that minimizes the delay time to get results for all the rounding modes defined in the IEEE Standards. An unified method to get the three bits(L, G, S)for the rounding is described. We also propose an unified guide line to determine the 1-bit shift for the post-normalization in the Floating-point$n_{addition}$ traction and multiplication. -
Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.
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Hardware to implement the parallelized Floating-point rounding algorithm is described. For parallelized additions, we propose an addition module which has carry selection logic to generate two results accoring to the input valuse. A multiplication module for parallelized multiplications is also proposed to generate Sum and Carry bits as intermediate results. Since these modules process data in IEEE standard Floatingpoint double precision format, they are designed for 53-bit significands including hidden bits. Multiplication module is designed with a Booth multiplier and an array multiplier.
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In this paper, a comparative study is presented to evaluate the addition architecture of the high-speed checksum module in TCP/IP processing. In order to speed up TCP/IP processing, H/W implementation offers concurrent and parallel processing to yield high speed computation, with respect to S/W implementation. This research aims at comparing two addition architectures of checksum module, which is the major botteleneck in TCP/IP processing. The 16-bit and 8-bit byte-by-byte addition architecture are implemented by the full custom design, and compared, in analytical and experimental manner, from standpoint of space and performance. For LG
$0.6\mu\textrm{m}$ TLM process, the 8-bit addition implementation requires the area, 1.3 times larger than the 16-bit one, and it operates at 80MHz while the 16-bit one runs by 66MHz. -
본 논문은 FLEX 디코더에서 필요한 심볼 클럭을 생성하기 위한 심볼 동기 알고리즘을 제안하고, 제안한 알고리즘을 기본으로 한 심볼을 동기회로의 설계에 관한 것이다. 제안한 알고리즘은 조-만 게이트 동기 (ELGS:Early-Late Gate Synchronization)기법을 이용하고 있다. VHDL(VHSIC Hardware Description Language)로 설계된 심볼 동기회로는 Synopsys 툴을 이용하여 기능레벨의 시뮬레이션을 수행하였고, Altera MAX+plus II를 이용하여 타이밍 분석을 수행하였다. 실험 결과로부터 Source unit와 FLEX 디스코더와의 시스템 동기가 정확히 이루어짐을 확인하였다.
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In this paper, current conveyor building block is introduced and CMOS realization of this block is given. The input-impedance characteristics, current-transfer characteristics and voltage-transfer characteristics of this proposed current conveyor circuit are given. This characteristics of the CMOS current conveyor circuit is useful of the various applications which require a wideband. Using the Spice tool, the circuit is designed and the characteristics of CMOS current conveyor circuit is considered. Finally, refer to the simple applications.
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In this paper the cellular neural networks with annealing capability is designed. The annealing capability helps the networks escape from the local-minimum points and quickly search for the global-minimum point. A 6
$\times$ 6 CNN chip is designed using a$0.8\mu\textrm{m}$ CMOS technology, and the chip area is 2.89mm$\times$ 2.89mm. The simulation results for hole filling image processing show that the general CNN has a local-minimum problem, but the annealed CNN finds the global-minimum solutions very efficiently. -
This paper proposes a efficient algorithm of letter-box converter using 4:3 decimation algorithm. To display 16:9 wide images on a 4:3 screen, there is need to convert the 16:9 wide images. The letter-box converter is designed with multiplierless architecture. We have modeled the letter-box converter in verilog-HDL and verified to show little difference between the original image and the converte image.
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A new simplified circuit model for the switching noise analysis of the complicated multi-layer IC package is developed. The current flowing mechanism on the ground and power planes of the package is simplified by using the dependent current soures and partial plane circuit model. The methodology is very cost-efficient as well as accurate. It is demonstrated that the nosie based on the simplified circuit model has an excellent agreement with that of the complicated full circuit model. However, the simplified model takes only 5 minutes for the switching noise simulation, while the full circuit model takes more than 4 hours.
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Package strutures for RF circuit design are characterized and their equivalent circuitsare developed. The circuit parameters are extracted by using the commercial 3-dimensional field solver. The circuit models are verified by using the full-wave analysis in the RF region. It is demonstarted with the developed circuit models that the packages have substantial effects on the RF circuit performances.
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Power Dissipation and circuit speed become the most importance parameters in VLSI system maximum power dissipation for VLSI system design. We remodeled CMOS inverter according to the operating region, saturation region or linear regin, and calculate maximum power dissipation point of CMOS inverter. The result of proposed maximum power dissipation model compared with those from SPICE simulation which results that the proposed maximum power dissipation model has the error rate within 10% to SPICE simulation.
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This paper proposes a new topology-based partition method for reconfigurable FPGA systems whose components nd the number of interconnections are predetermined. Here, the partition problem must also consider nets that pass through components such as FPGAs and routing devices to route 100%. We formulate it as a quadratic boolean programming problem suggest a paritition method for it. Experimental results show 100% routing, and up to 15% improvement in the maximum number of I/O pins.
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This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.
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Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.
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This paper describes implementation of a highlevel graphic design entry tool operating on X Window system The proposed design entry tool includes visual schematic entry, hierarchical modeling ability and VHDL source code generation. Experimental results show the efficiency of the proposed design system
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In this paper, a simple low-power current-mode CMOS wotage reference circuit is proposed. The reference circuit of enhancement-mode MOS transistors and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a threshold voltage. The designed circuit has been simulated using a
$0.65\mu\textrm{m}$ n-well CMOS process parameters. The simulation results show that the reference circuit has a temperature coefficient less than$7.8ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.079%/V for a temperature range from$-30^{\circ}C$ to$130^{\circ}C$ and a VDD range from 4.0V to 12V. The power consumption is 105㎼ for VDD=5V and$T=30^{\circ}C.$ The proposed reference circuit can be designed to generate a wide range of reference voltages owing to its current-mode operation. -
In this paper, we propose the bus coding technique for low power consumption. For CMOS circuit most power is dissipated as dynamic power for charging and discharging node capacitances.Though the I/O and bus are likely to have the very large capacitances associated with them and dissipate much of the power dissipated by an IC, they have little beenthe special target for power reduction. The conventional Bus-Invert coding method can't decrease the peak power dissipation by 50% because the additional invert signal line can invoke a transition at the time when Bus-Invert coding isn't used to code original bus data. The proposed technique always constraints the Hamming distance between data transferred sequentially to be below the half of the bus width, and thus decrease the I/O peak power dissipation and the I/O average power dissipation.
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In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP application, all of multiplier products were not used, but only upper bits of rpoduct were used. Kidambi proposed truncated unsigned multiplier for this idea. In this paper, we abopt this scheme to Booth multiplier which can be used for real DSP systems. Also, zero input guarantees zero output that was not provided in the previous work.
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Conventional floating-point adders have one data-path that is used for all operations. This paper describes a floatingpoint adder eeveloped for low power consumption, which has three data-paths one of which is selected according to the exponent difference. The first is applied to the case that the absolute exponent difference (AED) of two operands is less than 1, and the second is for 1The architecture and circuit design of low voltage, high performance barrel shifter is proposed in this paper. The proposed architecture consists of two arrays for byte and bit rotate/shift to perform 32-bit operation and is preferred for even bigger data length as it can be adapted for 64-bit extention with no increase of number of stages. NORA logic structure was used for circuit implementation to achieve the best performance in terms of speed, power and area. The complicated cloking control has been resolved with the ingenious design of clock dirver. The circuit simulation results in 3.05ns delay, 9.37㎽ power consumption at 1V, 160MHz operation when its implemented in low power
$0.5\mu\textrm{m}$ CMOS technology.In this paper, the PLL(Phase-Locked Loops) for low voltage and high speed operation is described. In other to obtaining above objects, new CMOS circuit technologies have been used in the each block circuit of PLL. It operates with a lock range from 110 up to 700 MHz and has a peak to peak jitter of 50 ps at operating frequency of 250 MHz. It was fabricated in a$0.6\mu\textrm{m}$ CMOS technology and dissipated 45 mW from a single 3.3V.The modern multimedia applications which are video processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the prosposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process imae data on the high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33MHz.본 논문은 VSB 전송방식의 HDTV 수신기에 입력되는 신호의 위상잡음 및 이득오차를 없애주는 위상 추적 루프를 설계하였다. 위상 추적 루프는 VSB 신호가 가지는 신호점과 입력된 I 채널의 표본화된 데이터를 이용하여 신호점들의 Q 채널 성분을 추정한 다음 복소곱셈기를 이용하여 입력신호와 곱합으로써 위상의 에러값을 보상하는 구조로 되어 잇다. 위상오차를 검출하는 알고리즘으로 시그늄 함수를 이용함으로써 하드웨어의 부담을 줄이면서 넓은 선형영역을 가질 수 있게 되어 우수한 추적 성능을 가지는 위상 추적 루프를 구현하였고 소프트웨어 심류레이션을 통하여 제시한 알고리즘의 효율성을 입증한 후 ASIC으로 구현하였다.In this paper, we propose a new architecture of the PN code acquistion system which has some shared blocks in order to reduce the hardware complexity. The proposed system has an energy calculation block which is shared by two active correlators. Our system is designed suitable for IS-95 based CDMA PCS. The new architecture was designed and simulated using VHDL. Also, We implemented it with Altera FPGA, and verified our system. The gate count is about 7,500. Our proposed architecture is also useful for multi-carrier system which uses the multiple searcher.This paper presents an efficient hardware architecture of demodulating fingers to demodulate the multi-path propagating signals in MC-CDMA Mobile System. We design a new architecture of demodulating fingers which share the single arithmetic unit to reduce the hardware complexity. This arithmetic unit performs MAC(Multiplication and Accumulation) operations of all demodulating fingers. The proposed architecture is suitable for Is-95 based CDMA PCS system. Three demodulating fingers for MC-CDMA which demodulate 7 channels contain about 42K logic gates. Our proposed system is shown to be very useful for Multi-Code CDMA system in which several channels are demodulated simultaneously.BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for$0.6\mu$ 1-poly, 3-matal CMOS technology.A CMOS RF bandpass amplifier which performs both functions of low-noise amplifier and bandpass filter is designed for the application of 1.9 ㎓ RF front-end in wireless receivers. The positive-feedback Q-enhancement technique is used to overcome the low gain and low Q factor of the bandpass amplifier. The designed bandpass amplifier is simulated with HSPICE and fabricated using HYUNDAI$0.8\mu\textrm{m}$ CMOS 2-poly 2-metal full custom process. Under 3 V supply voltage, results of simulation show that the CMOS bandpass amplifier provides the power gain 23dB, noise figure 3.8 dB, and power dissipation 55mW.A new architecture for high-speed implementation of adaptive decision-feedback equalizer (ADFE) applicable to wide-band digital wireless modems is described. Rather than using conventional two's complement arithmetic, a novel complex-valued filter structure is devised, which is based on redundant binary (RB) arithmetic. The proposed RB complex-valued filter reduces the critical path delay of ADFE, as well as leads to a more compact implementation than conventional methods. Also, the carry-propagation free (CPF) operation of the RB arithmetic enhances its speed. To demonstrate the proposed method, a prototype chip set is designed. They are designed to contain two complexvalued filter taps along with their coefficient updating circuits, and can be cascaded to implement loger filter taps for high bit-rate applications.This paper presents a design of special hardware developed for enhancing the floating-point power operations which are actively used at the lighting stage to calculate the specular term in 3D graphics geometry engines. The power operation takes just 4 cycles in our floating-point multiplier while it takes about 100-200 cycles in conventional floating-point units. Although an approximation algorithm is employed in the power operation to reduce the hardware complexity required, the error of power value from the developed floatingpoint multiplier is so minimal that no difference can be found by human eyes.본 논문에서 최적화이론이란 이 논문에서 두 개의 회로를 비교하고 트랜지스터의 개수를 적게 사용하여 전력소비를 줄일 수 있었고, 면적을 적게 축소하였다. 그리고 입출력에서 사용하는 제어는 크게 두 개로 나누었다. 첫 번째로 인버터를 사용해서 순차적으로 진행하도록 한 파이프라인의 회로를 설계하였고, 두 번째로 논리회로를 이용해서 n개의 MUX를 동시에 동작하도록 제어하였다. 두 개의 회로에서 트랜지스터의 개수와 반도체 칩의 면적 그리고 소비전력을 비교하여본다.In this paper, we propose the new hardware architecture which implements the stereo matching algorithm using the dynamic programming method. The dynamic programming method is used in finding the corresponding pixels between the left image and the right image. The proposed MOEPE(Merged Odd-Even PE) architecture operates in the systolic manner and finds the disparities from the intensities of the pixels on the epipolar line. The number of PEs used in the MOEPE architecture is the number of the range constraint, which reduced the number of the necessary PEs dramatically compared to the traditional method which uses the PEs with the number of pixels on the epipolar line. For the normal method by 25 times. The proposed architecture is modeled with the VHDL code and simulated by the SYNOPSYS tool.A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the$0.35\mu\textrm{m}$ CMOS model parameters.New capacitance modeling and transient analysis for multi-layer interconnects with shielding effect are presented. The upper layer capacitances with under-layer shielding lines are represented by introducing a filling factor η which can be defined as the ratio of upper-layer line length to the total under-layer line width. The upper-layer effective self capacitances considering two extreme cases which the underlayer metals are assumed as a ground or as a Vdd are modeled. The signal transient analysis with shielding effect model is performed.멀티미디어 데이터를 아날로그 방식보다는 디지털 방식으로 처리하게 되면 여러 면에서 이득을 볼 수 있다. 멀티미디어 데이터를 디지털 방식으로 처리하는 방법 중 범용프로세서에서 멀티미디어 명령어에 의해 처리하게 되면 flexibility를 증가시키며 효율적으로 프로그램할 수 있다. 본 논문에서는 범용 프로세서 안에서 멀티미디어 데이터를 효율적으로 처리할 수 있는 명령어 집합 구조와 이를 수행할 수 있는 프로세서의 구조를 제안하고 이를 HDL(Hardware Description Language)로 동작레벨에서 기술하고 시뮬레이션 하였다. 제안된 멀티미디어 명령어는 특성에 따라 8개의 그룹에 총 55개의 명령어로 구성되며 64비트 데이터 안에서 각각 8비트의 8바이트, 16비트의 4하프워드, 32비트의 2워드의 부워드(subword) 데이터들을 병렬 처리한다. 모델링된 프로세서는 오픈아키텍쳐(Open Architecture)인 SPARC V.9 의 정수연산장치(Integer Unit)에 기반을 두었으며 하바드 구조를 지닌 5단 파이프라인 RISC 형태이다.We describe a design of a simple but efficient floatingpoint processing architecture expoiting concurrent execution of scalar instructions for high performance in general-purpose microprocessors. This architecture employs 3 stage pipeline asyncronously working with integer processing unit to regulate instruction flows between two arithmetic units.This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256$\times$ 256 lenna image has been simulated using IDL(Interactive Data Language). The 2-D array structured BDFA for the 2-D filter has been modeled and simulated using VHDL.We designed a DSP core simulator with C language, that is able to simulate 5-stage pipelined DSP core, named YS-DSP. It can emulate all 5 stage pipelines in the DSP core. It can also emulate memory access, exception processing, and DSP parallel processing. Each pipeline stage is implemented by combination of one or more functions to process parts of each stage. After modeling and validating the simulator, we can use it to verify and to complement the DSP core HDL model and to enhance its performance.This paper describes a 72-word by 32-bit 2-read/1-write multi-port register file, which is suitable for 32-bit RISC/DSP microprocessors. To minimize area and achieve high speed, advanced single-ended sense amplifiers are used. Each part of circuit is optimized at transistor level. The verification of functionality and timing is performed using HSPICE simulations. After modeling and validating the circuit at transistor level, it was laid out in a 0.6um 1-poly 3-metal layer CMOS technology. The simulation results show maximum operating frequency is 179MHz in worst case conditions. It contains 27,326 transistors and the size is 3.02mm by 2.20mm.We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.we propose the Walsh-Hadamard Transform adaptive filter with time-varying step size. The performance of the proposed algorithm is evealuated in system identification where computer simulations are performed for both time-invariant and time-varying system. It is shown that the proposed algorithm produces good results compared with similar algorithms under different conditions, particularly in case of time-varying circumstance.광대역 능동잡음제거는 수 백개의 적응필터 탭 수를 갖는다. 탭 수가 긴 적응필터는 많은 계산량이 요구된다. 본 논문에서는 적응계수 벡터가 서브밴드로 계산되는 M-채널 QMF 필터뱅크와 적응필터를 이용한 자동차 소음제거 모델을 제안한다. 분해 필터뱅크와 합성 필터뱅크는 cosine-modulated pseudo QMF 필터를 사용한다. 오차경로의 전달특성을 온라인 인식하기 위한 기준신호는 적응필터의 출력신호와 저주파대역의 서브밴드 출력신호와의 차신호를 사용한다. 따라서 제안한 자동차 소음제거 모델은 계산량이 적고 수렴속도가 빠른 견실한 시스템이 되도록 제안한다.Adaptive nois canceller can extract the noiseremoved spech in noisy speech signal by adapting the filter-coefficients to the background noise environment. A kind of LMS algorithm is one of the most popular adaptive algorithm for noise cancellation due to low complexity, good numerical property and the merit of easy implementation. However there is the matter of increasing misadjustment at voiced speech signal. Therefore the demanded speech signal may be extracted. In this paper, we propose a fast and noise robust wavelet packet adaptive noise canceller with NLMS-SUM method LMS combined algorithm. That is, we decompose the frequency of noisy speech signal at the base of the proposed analysis tree structure. NLMS algorithm in low frequency band can efficiently dliminate the effect of the low frequency noise and SUM method LMS algorithm at each high frequency band can remove the high frequency nosie. The proposed wavelet packet adaptive noise canceller is enhanced the more in SNR and according to Itakura-Satio(IS) distance, it is closer to the clean speech signal than any other previous adaptive noise canceller.In this paper we propose a new efficient generalized sidelobe canceller(GSC) algorithm, using the efficient frequency domain LMS algorithm, which has much less weights to update. We only update part of all the weights according to magnitude of each frequency bin. So, the new proposed GSC algorithm, which is called censored GSC(C-GSC), can greatly reduce the computational complexity.This paper presents a new computationally efficient adaptive algorithm for blind signal separation, which is able to recover the narrowband source signals in the presence of cochannel interference without a prior knowledge of array manifold. We derive a new blind signal separation algorithm using the Natural gradient 〔1〕from an information-theoretic approach. The resulting algorithm has the Bussgang property which has been widely used in blind equalization 〔12〕. Extensive computer simulation results comfirm the validity and high performance of the proposed algorithm.A Novel Stop-&-Go Algorithm which incorporate a Bank structure for blind equalization is investigated in this paper. 16-QAM and$\pi/4-DQPSK$ modulation used in this paper. A Proposed novel algorithm of characteristic is high speed transfer by implementation of the equalization algorithm with less computations capacity. The computer simulations result reveal that the proposed Novel Stop-&-Go shows the comparable performance to the conventional Stop-&-Go, while requiring much less computations.4채널 입력으로부터 입력되는 오디오를 압축,복원,저장, 전송하는 ㅅ스템을 설계한다. 이러한 시스템은 보안 시스템 중에서 특정 센서로부터 alarm 신호를 디지털 데이터로 변환한 후, 압축시켜 저장하고 동시에 압축된 오디오 데이터를 비디오 데이터와 통합하여 하나의 스트림으로 만들어 통신망으로 보내주는 시스템에 적용된다. 이러한 시스템의 구조를 간단히 설명하면 아날로그 음성 신호를 디지털 음성 data로 변환하기 위해 OKI사의 MSM 7570L-91이라는 ADPCM codec을 사용하였고 ADPCMcodec을 거쳐 나온 ADPCM 데이터를 64Mbyte SDRAM에 저장하였다가 FIFO를 거쳐서 통신망으로 전송을 한다. 복원은 SDRAM에 저장된 ADPCM 데이터를 MSM 7570L-01을 거쳐 아날로그 신호로 변환한 후 엠프를 거쳐 스피커로 출력을 하게 된다.Considerable research in the last three decades has examined the problem of enhancement of speech degraded by additive background noise. We compare traditional methods such as spectral subtraction and Wiener filter, recently proposed psychoacoustic model based methods such as perceptual filter and noise suppression in EVRC in terms of performance and complexity.차세대 DVD system의 audio 규격인 Dolby AC-3를 구현하는 방법으로 DSP 프로세서인 TMSC80을 사용하여 실시간 처리 가능한 하드웨어 바탕의 firmware 소프트웨어를 개발하는 방법으로 구현하고자 한다. 본 논문에서는 먼저 TMS320C80을 바탕으로 한 하드웨어 구현에 관해 논의한다. 하드웨어의 구조는 TMS320C80과 시스템 메모리로의 DRAM, 오디오 입력부인 ADC, 입력 데이터를 효과적으로 사용하기 위한 FIFO menory, 오디오 출력용인 dac, 디버깅 및 통신포트로 USB, RS-232,LPT와 MPEG-2 encoding보드 등 다른 보드와 연계를 위한 local-bus를 위한 dual port ram으로 구성된다. 오디오 입력은 최대 24bit 48kHz sampling까지 받을 수 있다.Real-time implementation of Conjugate-Structure Algebraic CELP(CS-ACELP) is presented. ITU-T Study Group(SG) 15 has standardized the CS-ACELP speech coding algorithm as G.729. A real-time implementation of the CS-ACELP is achieved using 16 bit fixed point DSP16210 Digital Signal Processor (DSP) of Lucent Technologies. The speech coder has been implemented in the bit-exact manner using the fixed point CS-ACELP C source which is the part of the G.729 standard. To provide a multi-channel vocoder solution to digital communication system, we try to minimize the complexity(e.g., MIPS, ROM, RAM) of CS-ACELP. Our speech coder shows 15.5 MIPS in performance which enables 4 channel CS-ACELP to be processed with one DSP16210.본 논문은 Digital Audio Compression(AC-3) Standard 인 A-52를 기반으로 하였으며 Borland C++3.1 Compiler를 사용하여 AC-3 Decoding Algorithm 구현하였다. Input Stream은 DVD VOB File에서 AC-3 Stream만을 분리하여 사용하며 최종 출력은 16 Bit PCM File이다. AC-3의 Frame구조는 Synchronization Information, Bit Stream Information, Audio Block, Auxiliary Data, Error Check로 구성된다. Aduio Block 은 모두 6개의 Block으로 나뉘어져 있다. BSI와 Side Information을 참조하여 Exponent를 추출하여 Exponent Strategy에 따라 Exponent를 복원한다. 복원된 Exponent 정보를 이용하여 Bit Allocation을 수행하여 각각의 Mantissa에 할당된 Bit수를 계산하고 Stream으로부터 Mantissa를 추출한다. Coupling Parameter를 참조하ㅕ Coupling Channel을 Original Channel로 복원시킨다. Stereo Mode에 대해서는 Rematrixing을 수행한다. Dynamic Range는 Mantissa와 Exponent의 Magnitude를 바꾸는 것으로 선택적으로 사용할 수 있다. Mantissa와 Exponent를 결합하여 Floating Point coefficient로 만든 후 Inverse Transform을 수행하면 PCM Data를 얻을 수 있다. PC에서 듣기 위해서는 Multi Channel을 Stereo나 Mono로 Downmix를 수행한다. 이렇게 만들어진 PCM data는 PCM Data를 재생하는 프로그램으로 재생할 수 있다.This paper analyzes the dynamic spars algebraic codebook used to model a residual signal and proposes a new algebraic codebook structure as well as a searching process with improved performance. The proposed algorithm improves the disadvantage of algebraic codebook without increased computation. First, this paper makes it possibel to select various pulse amplitudes differently from the conventional method which looks up the sign bit simply. In addition, two pulses are made to be selected on the same track. For speech quality on the telephone line 5.6kbps speech coder using the proposed algorithm was equivalent to the 6.3kbps MP-MLQ in the viewpoint of subjective speech quality. However, speech degradation was caused a little compared to the MP-MLQ where MNRU 1=15dB.The pre-emephasis filter as the conventional method emphasizes all components of high frequency that reflects the speaker characteristics. However this filter don't show the auditory characteristics of speaker's speech. In order to emphasize the perceptual characteristics, we propose the speaker recognition system that uses the perceptual weighting as the preprocessor because the Auditory characteristic of human is sensitive to the formant peaks. This filter has the characteristcs that both deemphasizes the low-formants and emphasizes the high formants. As a result of the proposed method, we improve the total recognition rate 1.7% better than the conventional method.Phase control methods are used to expand the sound image in general AV system. However, these methods are effective only to the signal under 1kHz, and the listener must be located in front center of the speaker system. In this paper, we realize the realtime processing system in which phase shifting method is dominant at low frequency and precedence effect is dominant at high frequency. Two sound cards are used to process the audio signal in realtime with 16 bits stereo channel of 44.1 kHz sampling frequency. And the analog circuit is designed to process the phase shifting. In experiments the usefulness of the proposed stereo system is confirmed.Many signal processing methods of widening the sound image for spatial impression have been studied. Most typical methods of widening the sound image are related to the phase shifting and precedence effect. However, these methods are not effective in center sound image. As listener's position moves from center to outside, the center sound image is shifted to the speaker. That is to say, the directional localization of center sound image is unstable. In this paper, we propose a television audio system including center speaker, and analyze the role of center speaker using theory of Makida and precedence effect. In experiments, we confirm the usefulness of the center speaker for the stability of center sound image.In television stereo system, to produce the sound image for spatial impression is too difficult because of the narrow distence between two speakers. A method of widening the sound image using precedence effect was introduced but it didn't work effectively in low frequency band. In this paper, we propose a new method to produce an expanded sound image in full band of audio requency in band sound is expanded by phase shifting method and a higher frequency band sound is expanded by reflection. In simulation and experiment, the proposed system guarantees useful effect of sound image expansion in television stereo system.In television stereo system, to produce a realistic sound effect is very difficult because the distance between stereo speakers is very narrow. Many signal processing methods of widening the sound image for spatial impression have been studied. One of the methods of widening the sound image is using the Precedence Effect by reflected sound. However, this method does not work effectively in lower frequencies because of directivity of a speaker. In this paper, we propose an effective method of expanding stereo image using Precedence Effect and Phase Shifting method to produce a whole band frequency sound expansion. In experiments, we confirm the usefulness of the proposed stereo sound image expansion system.Three-dimensional(3-D) sound is a technique for generating or recreating sounds so they are perceived as emanating from locations in a three-dimensional space. Three dimensional sound has the potential of increasing the feeling of realism in music or movie soundtracks. Three-dimensional sound effects depend on psychoacoustic spectral and phase cues being presented in a reproduced signal. In this paper we propose an effective algorithm for the sound image expansion in television system using stereo image enhancement techniques. Compared to the other techniques of three-dimensional sound, the proposed algorithm use only two speakers to enhance the sound image expansion, while maintaining the original sound characteristics.In speech synthesis, LF model is widely used for excitation signal for voice source coding system. But LF model does not represent the harmonic frequencies of excitation signal. We propose an effective method which use sinusoidal functions for representing the harmonics of voice source signal. The proposed method could achieve more exact voice source waveform and better synthesized speech quality than LF model.본 논문에서는 최근들어 널리 연구되고 있는 다해상도 신호해석 방법인 웨이브렛 변환, 웨이브렛 패킷, 그리고 코사인 패킷 알고리듬을 음성개선에 이용하여 각각의 성능을 비교하였으며, 또한 이를 기존의 스펙트럼차감법의 성능과 비교 분석 하였다. 성능비교의 척도로는 SNR과 ㅋ스트랄 거리를 이용하였다. 실험결과 SNR면에서는 코사인 패킷이 가장 좋은 결과를 보였다. 그리고 ㅋ스트랄 거리의 경우 코사인 패킷과 웨이브렛 패켓이 훨씬 나은 결과를 보였으며 주관적인 청취결과 역시 코사인 패킷이 가장 좋은 결과를 보였고, 기존의 스펙트럼 차감법은 musical noise의 영향으로 인해 상대적으로 다른 방식에 비해 합성음의 음질이 많이 떨어짐을 확인할 수 있었다.Hidden Markov Model (HMM) is the most widely used method in speech recognition. In general, HMM parameters are trained to have maximum likelihood (ML) for training data. This method doesn't take account of discrimination to other words. To complement this problem, this paper proposes a word verification method by re-recognition of the recognized word and its similar word using the discriminative function between two words. The similar word is selected by calculating the probability of other words to each HMM. The recognizer haveing discrimination to each word is realized using the weighting to each state and the weighting is calculated by genetic algorithm.This paper introduced a scheme for finding the relationships between the measurements and tracks in multi-target tracking (MTT). We considered the relationships between targets and measurements as MRF and assumed a priori as a Gibbs distribution. An energy function is defined over the measurement space, as accurately as possible so that it may incorporate most of the important natural constraints. To find the minimizer of the energy function, we derived a new equation of closed form.In this paper, we propose an optimal feature extraction method for normally distributed multiclass data. We search the whole feature space to find a set of features that give the smallest classification error for the Gaussian ML classifier. Initially, we start with an arbitrary feature vector. Assuming that the feature vector is used for classification, we compute the classification error. Then we move the feature vector slightly and compute the classification error with this vector. Finally we update the feature vector such that the classification error decreases most rapidly. This procedure is done by taking gradient. Alternatively, the initial vector can be those found by conventional feature extraction algorithms. We propose two search methods, sequential search and global search. Experiment results show that the proposed method compares favorably with the conventional feature extraction methods.This paper analyzes the characteristics of wide-band one-shot beam formed by using all sensors of array at once, as variation of weighting width. Gaussian function is applied to each sensor as a role of weighting. As the results of the simulation for nested linear array having 17 sensors for each octave, as the width goes wider the directivity index(DI) becomes lower but more even and the variation of beamwidth becomes smaller. It is confirmed, therefore, that weighting width is carefully decided in consideration of DI level, DI stability and the beamwidth.The HMM-Net is an architecture for a neural network that implements a hidden Markov model (HMM). The architecture is developed for the purpose of combining the discriminant power of neural networks with the time-domain modeling capability of HMMs. Criteria used for learning HMM-Net classifiers are maximum likelihood (ML), maximum mutual information (MMI), and minimization of mean squared error(MMSE). In this paper we propose an efficient learning method of HMM-Net classifiers using hybrid criteria, ML/MMSE and MMI/MMSE, and report the results of an experimental study comparing the performance of HMM-Net classifiers trained by the gradient descent algorithm with the above criteria. Experimental results for the isolated numeric digits from /0/ to /9/ show that the performance of the proposed method is better than the others in the respects of learning and recognition rates.We propose a structural learning method of MLP classifiers for a given application using PfSGA (parameter-free species genetic algorithm), which is a combining of species genetic algorithm(SGA) and parameter-free genetic algorithm(PfGA). experimental results show that PfSGA can reduce the learing time of SGA and has no influence of parameter values on structural learning. And we also convince that PfSGA is more efficient than the other methods in the aspect of misclassification ratio, learning rate, and complexity of MLP structure.This paper proposes an efficient time series prediction of the nonlinear dynamical discrete-time systems using multilayer neural networks of a hybrid learning algorithm. The proposed learning algorithm is a hybrid backpropagation algorithm based on the steepest descent for high-speed optimization and the dynamic tunneling for global optimization. The proposed algorithm has been applied to the y00 samples of 700 sequences to predict the next 100 samples. The simulation results shows that the proposed algorithm has better performances of the convergence and the prediction, in comparision with that using backpropagation algorithm based on the gradient descent for multilayer neural network.In this paper, we propose a new learning algorithm for multilayer neural networks. In the error backpropagation that is widely used for training multilayer neural networks, weights are adjusted to reduce the error function that is sum of squared error for all the neurons in the output layer of the network. In the proposed learning algorithm, we consider each output of the output layer as a function of weights and adjust the weights directly so that the output neurons produce the desired outputs. Experiments show that the proposed algorithm outperforms the backpropagation learning algorithm.HCI(human computer interface) technologies have been often implemented using mouse, keyboard and joystick. Because mouse and keyboard are used only in limited situation, More natural HCI methods such as speech based method and gesture based method recently attract wide attention. In this paper, we present multi-modal input system to control Windows system for practical use of multi-media computer. Our multi-modal input system consists of three parts. First one is virtual-hand mouse part. This part is to replace mouse control with a set of gestures. Second one is Windows control system using speech recognition. Third one is Windows control system using gesture recognition. We introduce neural network and HMM methods to recognize speeches and gestures. The results of three parts interface directly to CPU and through Windows.This paper presents a new signature verification technique that not only maximally allows variations in signatures of each person, but also discriminates effectively forgeries from true signatures. The signature verification system is designed to detect unstable portions in signatures of same person, and to give large weight on the portion that is difficult to imitate and plays an important role in signature verification. In registration mode, the system extracts subpatterns from training samples and analizes their consistency and singularity by calculating the variance and complexity of this portion. In verification mode, the system verifies a input signature by comparing corresponding subpatterns with the weights of reference subpatterns.In this paper, we discuss the identification of a chaotic system using chaotic neural networks. Because of selfconnections in neuron itself and interconnections between neurons, chaotic neural networks identifiers show good performance in highly nonlinear dynamics such as chaotic system. Simulation results are presented to demonstrate robustness of chaotic neural networks identifier.Several neural networks have been successfully used to classify complex patterns such as handwritten numerals or words. This paper describes the discrimination of totally unconstrained handwritten numerals using the proposed chaotic neural network (CNN) to improve the recognition rate. The recognition system in the paper consists of the preprocessing stage to extract features using Kirsch mask and the classification stage to recognize numerals using the CNN. In order to evaluate the performance of the proposed network, we performed the recognition with unconstrained handwritten numeral database of Concordia university, Canada. Experimental results show that the CNN based recognizer performs higher recognition rate than other neural network-based methods reported using same database.
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