대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1998년도 추계종합학술대회 논문집
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- Pages.707-710
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- 1998
DRAM의 저전력, 고속화에 따른 VDC 설계에 관한 연구
A Study on the Design of the Voltage Down Converter for Low Power, High Speed DRAM
초록
This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a
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