대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1998년도 추계종합학술대회 논문집
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- Pages.1097-1100
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- 1998
저전압, 고속동작을 하는 위상 동기 루프(PLL)의 설계
Design of PLL for Low Voltage and High Speed Operation
초록
In this paper, the PLL(Phase-Locked Loops) for low voltage and high speed operation is described. In other to obtaining above objects, new CMOS circuit technologies have been used in the each block circuit of PLL. It operates with a lock range from 110 up to 700 MHz and has a peak to peak jitter of 50 ps at operating frequency of 250 MHz. It was fabricated in a
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