Reconfigurable FPGA 시스템을 위한 위상기반 회로분할

Topology-Based Circuit Partitioning for Reconfigurable FPGA Systems

This paper proposes a new topology-based partition method for reconfigurable FPGA systems whose components nd the number of interconnections are predetermined. Here, the partition problem must also consider nets that pass through components such as FPGAs and routing devices to route 100%. We formulate it as a quadratic boolean programming problem suggest a paritition method for it. Experimental results show 100% routing, and up to 15% improvement in the maximum number of I/O pins.