Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
The Institute of Electronics and Information Engineers (IEIE)
- 기타
2003.07b
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Ni-silicide has low thermal stabiliy. This point is obstacle to apply NiSi to devices. So In this paper, we have studied for obtain thermal stability and analysis of dopant dependency of NiSi. And then we applied Ni-silicide to devices. To improvement of thermal stability, we deposit Ni70/Co10/Ni30/TiN100 to sample. Co midlayer is enhanced thermal stability of NiSi. Co/Ni/TiN, this structure show very difference between n-poly and p-poly in sheet resistance. But Ni/Co/Ni/TiN, structure show less difference. Also junction leakage is good.
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본 논문에서는 Cobalt interlayer 와 Titanium Nitride(TiN) capping layer를 Ni SALICIDE의 단점인 열 안정성과 sheet resistance 와 series 저항을 감소시키는데 적용하여 0.lum 급 CMOS 소자의 특성을 연구하였다. 첫째로, Ni/Si 의 interface 에 Co interlayer 를 증착하여 Nickel Silicide의 단점인 열 안정성 평가인 700℃, 30min의 furnace annealing 후에 낮은 sheet resistance와 누설전류를 줄일 수 있었다. 두번째로, TiN caping layer를 적용하여 실리사이드 형성시 산소와의 반응을 막아 실리사이드의 표면특성을 향상시켜 누설전류의 특성을 개선하였다. 결과적으로 소자의 구동전류 향상, 누설전류 저하, 낮은 면저항으로 소자의 특성을 개선하였다.
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본 논문에서는 N-type 기판에서 Nickel-Silicide를 적용하였을 경우에 나타나는 문제점과 PAI (Pre-amorphization Implant)의 효과에 대하여 알아보았다. N-type 기판에 RTP (Rapid Thermal Process)를 통하여 Nickel-Silicide 를 형성하게 되는데, 여기까지는 안정한 Nickel mono-Silicide (NiSi)가 형성됨을 확인하였다. 하지만 후속 열처리 공정 후 심한 응집 현상 (Agglomeration)과 이상 산화 현상 (Abnormal Oxidation Phenomenon), Silicide Island 등 열안정성 (Thermal Stability) 측면에서 여러 가지 많은 문제점들이 나타났다. 이 후속 열처리의 열안정성 취약점들을 극복하는 방안으로 Ge 및 N₂ PAI를 적용하였다. PAI를 적용하였을 경우에는 그렇지 않은 경우에 비하여 고온 열처리 후에도 면저항이 비교적 잘 유지되었으며, 두께가 얇고 안정한 Nickel-Silicide 특성을 확보할 수 있었다. 특히 Ge PAI 에 비하여 N₂ PAI 의 경우가 보다 특성 개선 효과가 크게 나타났다.
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Improvement in MOS fabrication technology have led to high-density high-performance integrated circuits with MOSFET channel lengths in the sub-micron range. For devices of the size, transistor characteristics become highly sensitive to effective channel length. We propose a new approach to extract the effective channel length of MOSFET by Capacitance-Voltage (C-V) method. Gate-to-Source, Drain capacitance (
$C_{gsd}$ ) are measured and the effective channel length can be extracted. In addition, compared to l/$\beta$ method and Terada method, which has been point out that it fails to extract the accurate effective channel length of the devices, we prove that our approach still works well for the devices with down to sub-micron regime.e. -
In this paper, we have investigated electrical characteristics of TRENCH GATE POWER MOSFET in the temperature range of 300K to 500K. The results of this study indicate that on-resistance and breakdown voltage increase with the temperature ,but drain current, threshold voltage and transconductance decrease with the temperature. Especially, it is observed that electrical characteristics are improved as numerical unit cells are increased.
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Experimental results are presented for gate oxide degradation and its effect on device parameters under negative and positive bias stress conditions using NMOSFET's with 3 nm gate oxide. The degradation mechanisms are highly dependent on stress conditions. For negative gate voltage, both hole- and electron-trapping are found to dominate the reliability of gate oxide. However, with changing gate voltage polarity, the degradation becomes dominated by electron trapping. Statistical parameter variations as well as the "OFF" leakage current depend on those charge trapping. Our results therefore show that Si or O bond breakage by electron can be another origin of the investigated gate oxide degradation.gradation.
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Density gradient method is used to analyze the quantum effect in MOSFET, Quantization effect in the poly gate leads to a negative threshold voltage shift, which is opposed to the positive shift caused by quantization effect in the channel. Quantization effects in the poly gate are investigated using the density gradient method, and the impact on the short channel effect of double gate device is more significant.
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This paper presents a Si power LDMOSFET for power amplifiers in the 1.8-2.2GHz frequency range for the base station of personal communication systems. To improve the cut-off frequency, the proposed Si power LDMOSFET has small gate to drain capacitance by shielding the electric fields with extended source electrode and forming the field oxide structure in drain region. The proposed Si power LDMOSFET can be used for a power amplifier and it has 32% of power added efficiency and 39.5dBm of output power when the supply voltage is 28V and the operating frequency is 1.9GHz.
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본 논문에서는 주파수 1∼7GHz 에서 게이트 바이어스가 □ 2.0 ∼ 2.0 V 일때 사용 가능한 축적형 버랙( accumulation mode varactor )의 RF 모델링 기법을 제안하였다. 기존의 모델링 기법은 가변 커패시터가 존재하는 부분에서 임피던스의 실수성분이 일정한 값을 가지는 것으로 모델링 하였으나 소자의 측정결과를 통하여 실수성분이 일정한 값이 아닌 주파수에 따라 변화하는 값임을 알았다. 이를 설명하기 위해서 기존의 모델링 기법에 커패시터와 저항을 하나씩 추가하여 새로운 모델을 구성하고 각각의 파라미터를 추출하였다.
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Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.
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10nm 이하의 두께를 갖는 얇은 SOI 층 위에서 우수한 동작 특성을 보이는 Fully-Depleted SOI nMOSFET 을 제작하였다. 게이트의 길이가 큰 경우에는 SOI 층이 얇지 않아도 좋은 특성을 보이지만, 게이트 길이가 100nm 이하에서는 Short Channel Effect 에 의한 특성 열화 때문에 SOI thin body 의 두께가 게이트 길이에 따라 같이 얇아져야 한다. [1] 100nm 게이트 길이 SOI-NMOSFET에서 10nm 이하 body 두께에 따라 Vth는 조금 상승했고, Subthreshold slope은 조금 개선되는 특성을 보였다. 또한, 45nm 게이트 길이와 3nm 로 추정되는 body 두께를 갖는 nMOSFET 에서 우수한 I-V 동작 특성을 얻었다.
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In this presentation, we investigated the abnormal subthreshold slope of the FD SOI MOSFETs upon the rapid thermal annealing. Based on subthreshold technique and C-V measurement, we deduced that the hump of the subthreshold slope comes from the abnormal D
$_{it}$ distribution after RTA. The local kink in the interface trap density distribution by RTA drastically degrades the subthreshold characteristics and mini hump can be eliminated by S-PGA.A. -
The electrical characteristics of Polysilicon Source/Drain SOI MOSFETs with high-k gate dielectrics.본 논문에서는 MOSFET source/drain 고체 확산 원으로써 도핑된 폴리 실리콘을 사용하였으며 확산 후 남은 폴리 실리콘은 elevated source/drain 역할을 하여 저항을 줄여 준다. 또한 제안 된 구조는 게이트 절연막 공정 이전에 확산 공정이 이루어 지기 때문에 후속 열처리에 취약한 고유전율 게이트 절연막 공정과 금속 게이트 공정에 적합한 공정으로 적합함을 보였다.
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This work investigates the device degradation p-channel PD SOI devices at various applied voltages as well as stress temperatures with respect to Body-Contact SOI (BC-SOI) and Floating-Body SOI (FB-SOI) MOSFETs. It is observed that the drain current degradation at the gate voltage of the maximum gate current is more significant in FB-SOI devices than in BC-SOI devices. For a stress at the gate voltage of the maximum gate current and elevated temperature, it is worth noting that the
$V_{PT}$ Will be decreased by the amount of the HEIP plus the temperature effects. For a stress at$V_{GS}$ =$V_{DS}$ . the drain current decreases moderately with stress time at room temperature but it decreases significantly at the elevated temperature due to the negative bias temperature instability. -
본 논문에서는 Porous poly-silicon cold cathode에 의해 전자를 방출하는 Ballistic electron surface-emitting display(BSD)의 전계방출 특성을 실험했다. BSD는 nanocrystalline을 둘러싼 산화막을 multi-tunneling한 전자에 의해 발광이 되는 mechanism이기 때문에 산화막의 두께를 변수로 두어 특성을 실험했다. 900℃에서 1시간에서 3시간까지 30분 간격으로산화 반응을 진행하였으며, leakage current와 emission current의 비로 효율을 나타내었을 때 1시간 30분 동안 산화 반응을 한 시료가 가장 좋은 특성을 나타내었다.
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Thin tin oxide film with nano-size particle was prepared on silicon substrate by hydrothermal synthetic method and successive sol-gel spin coating method. The fabrication method of tin oxide film with ultrafine nano-size crystalline structure was tried to be applied to fabrication of micro gas sensor array on silicon substrate. The tin oxide film on silicon substrate was well patterned by chemical etching upto 5
${\mu}{\textrm}{m}$ width and showed very uniform flatness. The tin oxide film preparation method and patterning method were successfully applied to newly proposed 2-dimensional micro sensor fabrication. -
An atomistic process modeling, Kinetic Monte Carlo simulation, has the advantage of being both conceptually simple and extremely powerful. Instead of diffusion equations, it is based on the definitions of the interactions between individual atoms and defects. Those interactions can be derived either directly from molecular dynamics, first principles calculations, or from experiment. In this paper, as a simple illustration of the kinetic Monte Carlo we simulate defects (self-interstitials and vacancies) diffusion after ion implantation in Si crystalline.
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In this paper, we report a molecular dynamics (MD) simulation of the ion implantation for nano-scale devices with ultra-shallow junctions. In order to model the profile of ion distribution in nanometer scale, the molecular dynamics with a damage model has been employed. As an exemplary case, we calculate the dopant profile during the ion implantation of B, As, and Ge.
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본 연구에서는 정전계 에너지를 이용하여 IPS-LCD의 화소와 각 전극간 정전용량을 엄정한 방법으로 계산하였다. 정전계 에너지는 전극의 유한한 크기로 인해 발생하는 측면 전장효과를 고려한 3차원 방향자와 전위분포를 시뮬레이션 함으로써 얻을 수 있었다. 수치해석 방법으로는 유한차분법을 사용하였다. 그 결과 IPS-LCD의 화소 정전용량과 게이트-공통전극간 정전용량은 구조적 특성으로 인해 기존의 TN-LCD와 비교하여 1/16배 가량으로 훨씬 더 작은 값을 나타냄이 확인되었다.
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We have successfully used hydrophobic direct-wafer bonding, along with H-induced layer splitting of Ge, to transfer 700nm think, single-crystal Ge films to Si substrates. Optical and electrical properties have been also observed on these samples. Triple-junction solar cell structures gown on these Ge/Si heterostructure templates show comparable photoluminescence intensity and minority carrier lifetime to a control structure grown on bulk Ge. When heavily doped p
$^{+}$ Ge/p$^{+}$ Si wafer bonded heterostructures were bonded, ohmic interfacial properties with less than 0.3Ω$\textrm{cm}^2$ specific resistance were observed indicating low loss thermal emission and tunneling processes over and through the potential barrier. Current-voltage (I-V) characteristics in p$^{+}$ Ge/pSi structures show rectifying properties for room temperature bonded structures. After annealing at 40$0^{\circ}C$ , the potential barrier was reduced and the barrier height no longer blocks current flow under bias. From these observations, interfacial atomic bonding structures of hydrophobically wafer bonded Ge/Si heterostructures are suggested.ested. -
We have studied PHEMTs optimization by means of fabrication of PHEMTs. All PHEMTs have been fixed with a gate length of 0.1
${\mu}{\textrm}{m}$ , a gate head size of 0.75${\mu}{\textrm}{m}$ , and two gate fingers. We have measured the characteristics of PHEMTs with variation of source-drain spacing, pad size, and gate width. As a result, we have found the enhanced characteristics of$I_{dss}$ ,$S_{21}$ ,$h_{21}$ ,$f_{T}$ ,$f_{max}$ , and$G_{ms}$ with increasing gate width. Also,$g_{m}$ has improved with decreasing source-drain spacing, and$S_{21}$ has improved with deceasing pad size.e.e.e.e. -
Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with pseudomorphic HEMTs. We have studied the calibration on the DC and RF characteristics of the MHEMT device using I
$n_{0.53}$ G$a_{0.47}$ As/I$n_{0.52}$ A1$_{0.48}$ As modulation-doped heterostructure on the GaAs wafer. For the optimized device performance simulation, we calibrated the device performance of 0.1-${\mu}{\textrm}{m}$ $\Gamma$ -gate MHEMT fabricated in our research center using the 2D ISE-DESSIS device simulator. With this calibrated parameter set, we have obtained very good reproducibility. The device simulation on the DC and RF characteristics exhibits good reproducibility for our 0.1-${\mu}{\textrm}{m}$ -gate MHEMT device compared with the measurements. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.ormance. -
본 논문에서 단거리전용통신(DSRC)용 OBE에 사용되는 5.8GHz 송신측 ASK와 PA를 one-chip화하여 MMIC로 설계를 및 제작하였다. 설계된 ASK-PA는 3V 단일 공급전원을 사용하였고, 능동 소자로서 GaAs MESFET을 사용하였다. ASK는 회로의 복잡도를 줄이기 위해 직접변조 방식을 채택하였고, 인접채널 간섭의 영향을 줄이기 위하여 드레인 제어 변조회로를 사용하였다. 또한 전력증폭기는 2단으로 하여 AB급으로 동작하도록 전압분배 바이어스회로로 구성하였다. 측정결과 3V의 공급전압에서 전체이득 20.63dB, 송신출력 7.8dBm으로 나타냈다. 공정은 ETRI 0.5㎛ GaAs MESFET 공정을 사용하였고, Chip size는 1.2mm×l.4mm이다.
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Characteristics analysis of Piezoelectric Thin Film SAW filter using Mg-doped GaN/Sapphire StructureThe epitaxially grown Mg-doped GaN thin film was prepared by MOCVD (Metal Organic Chemical Vapor Deposition) for a SAW(Surface Acoustic Wave) filter. Mg-doped GaN thin film had enough properties for a SAW filter which include crystallinity and morphology. The surface morphology and crystalline of the Mg-doped GaN thin films were characterized using AFM and an X-ray rocking curve. The SAW filter, which was fabricated by lift-off process and frequency response, was measured by HP 8753C network analyzer. Center frequency was 96.687 MHz and SAW velocity was 5801 m/s when wavelength(λ) was 60
${\mu}{\textrm}{m}$ . Insertion loss was over -10 dB, Q was factor over 200, and side lobe attenuation was over 22 dB which was suitable for use as a SAW filter. Electro-mechanical coupling coefficient (k$^2$ ) was calculated from the measured data. k$^2$ was from 1 % to 1.44 %. The fabricated SAW filter using Mg-doped GaN/sapphire structure has good qualities as a filter and will be used as a SAW filter for operating RF frequency. -
A direct parameter extraction method using several two-port parameter equations derived in cutoff and active bias modes has been studied to obtain an accurate Gummel-Poon BJT model. First, dc model parameters were extracted from slopes and y-axis intercepts of I-V curve and Gummel plot. The pad capacitances and junction capacitance parameters were determined by using measured S-parameter sets in the cutoff bias. The resistance and transit time parameters were extracted by using measured S-parameter sets in the active bias.
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A SiGe HBT MMIC differential VCO has been developed for C-band wireless LAN applications. The VCO produces -6.4 dBm output power at 4.75 GHz. The VCO exhibits a 490 MHz tuning range with control voltage from 0.5 V to 2.5 V. The phase noise of the VCO exhibits -106.5 dBc/Hz at 1 MHz offset from the 4.75 GHz carrier. The total current consumption of the VCO is 10 mA at a supply voltage of 3 V.
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Passivation Ledge's device is taken possession on one-side to the Emitter in this Paper. contact used in this paper Pt as Passivation Ledge of device to use Schottky Diode which has leitmotif, It is accomplished Current Modulation that we wish to do purpose using this device. Space Charge acts as single device which is becoming Passivation to know this phenomenon. This device becomes floating as well as Punched-through. V
$_{L}$ (Voltage for Ledge) = - 0.5V ~ 0.5V variable values , PD(Partially Depleted ; Λ>0), as seeing FD(Fully Depleted ; A = 0) maximum electric current gains and Gummel Plot of I-V characteristics (V$_{L}$ = 0.1/ V$_{L}$ = -0.1 ). Becomming Degradation under more than V$_{L}$ = 0.1 , less than V$_{L}$ =-0.05 and Maximum Gain(=98.617076 A/A) value in the condition V$_{L}$ = 0.1. A Change of Modulation is electric current gains by using Schottky Diode and Extrinsic Base PN Diode of Passivation Ledge to Emitter Depletion Layer in HBT of Gummel-Poon I-V characteristics and the RF wide-band electric current gains change the Modulation of CE(Common-Emitter) amplifier description, and it had accomplished Current Gain Modulation by Ledge Bias that change in high frequency and wide bands. wide bands.s. -
In this paper, we report our quantum mechanical approach for the analysis of FinFET in a self-consistent manner. The simulation results are carefully investigated for FinFET with an electrical channel length(Leff) of 30nm and with a fin thickness(Tsi) of 10~35nm. We also demonstrated the differences in the simulations for the classical and quantum-mechanical simulation approaches, respectively. These simulation results also imply that it is necessary to solve the coupled Poisson and Schrodinger equations in a self-consistent manner for analyzing the sub-30nm MOSFETS including FinFET.
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The theoretical and experimental current-voltage characteristics of Erbium silicided n-type Schottky barrier tunneling transistors (SBTTs) are discussed. The theoretical drain current to drain voltage characteristics show good correspondence and the extracted Schottky barrier height is 0.24 eV. The experimentally manufactured n-type SBTTs with 60 nm gate lengths show typical transistor behaviors in drain current to drain voltage characteristics. The drain current on/off ratio is about 10
$^{5}$ at low drain voltage regime in drain current to gate voltage characteristics. -
A simple fabrication method of self-aligned ridge waveguides with dielectric side buffers is demonstrated on +Z- cut LiNbO
$_3$ . The ridge waveguide is fabricated by a combination of the annealed proton exchange process and the proton-exchanged wet etching technique. The self-aligned process is achieved by wet etching of aluminum. -
This paper describes a high speed correlator that can acquire synchronization quickly. The existing addition algorithm is a binary adder tree architecture that will result in extremely slow speed of operation due to many levels of logic required for computation of correlation[2][3]. This paper suggests the new various architectures, which are systolic array architecture, simple pipeline architecture and block systolic array architecture[4][5]. The acquisition performance of the proposed architectures is analyzed and compared with the existing architecture. The comparison results show that the systolic array architecture and the block systolic array architecture reduce the timing delay up to 73% and 31%, respectively. And the results show that the simple pipeline architecture reduces the timing delay up to 53%..
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The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-
${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock. -
In this paper, a CMOS Tx RF/IF single chip for PCS applications is designed. The chip consumes 84mA from a 3V supply and the layout area without pads is 1.6mm
$\times$ 3.5mm. Simulation results show that the RF block composed of a SSB RF block and a driver amplifier exhibits a gain of 14.8dB and an OIP3 of 7dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. The designed circuits are under fabrication using a 0.35${\mu}{\textrm}{m}$ CMOS process. -
In this paper a FPGA implementation of WEP protocol is described. IEEE 802.11 specifies a wired LAN equivalent data confidentiality algorithm. WEP(Wired Equivalent Privacy) is defined as protecting authorized users of a wireless LAN from casual eavesdropping. WEP use RC4 algorithm for data encryption and decryption, also it use CRC-32 algorithm for error detection. The WEP protocol is implemented using Xilinx VirtexE XCV1000E-6HQ240C FPGA chip with PCI bus interface.
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본 논문에서는 traceback 동작 없이 decoding이 가능한 Modified Register Exchange 방식을 이용하여 이를 block decoding에 적용하는 비터비 decoding 방식을 제안하였다. Modified Register Exchange 방식을 block decoding에 적용함으로써 decision bit 들을 결정하기 위해 필요한 동작 사이클을 줄였고, block decoding을 사용하는 기존의 비터비 디코더보다 더 적은 latency 가지게 되었다. 뿐만 아니라, 메모리를 더 효율적으로 사용할 수 있으면서 하드웨어의 구현에 있어서도 복잡도가 더 감소하게 된다. 제안된 방식은 같은 하드웨어 복잡도로도 메모리의 감소 또는 latency 의 감소에 중점을 둔 설계가 가능하다.
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The PCI 2.2 spec introduces Delayed Transaction mechanism to improve system performance for target device with slow local bus. But this mechanism has some restriction since target device doesn't know prefetch data size. So, we propose a new mechanism, which target device prefetch exact data on local bus, to improve data rate on PCI or local interface. The simulation results showed that the proposed mechanism more improves system performance than the Delayed Transaction mechanism.
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Today's and tomorrow's processors and I/O devices are demanding much higher I/O bandwidth than PCI 2.3 or PCI-X can deliver and it is time to engineer a new generation of PCI to serve as a standard I/O bus for future generation platforms. According to this demand the PCI SIG proposed PCI Express. This paper describes about the design of PCI Express Behavioral Model. A Behavioral Model enables the designers to test whether the design specifications are met by performing computer simulations rather than experiments on the physical prototype. In the proposed Model, we can verify whether our design concept satisfies the PCI Express functional protocol.
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New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.
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This paper defines an algorithmic description language in cycle-accurate level which can be used to design hardware components. The proposed language is less complex and more flexible than VHDL language. In that the language includes C-like control flow descriptions and brief timing information(i.e. clock cycle boundaries) indicated by 'wait_edge' statements. We generate RTL VHDL codes from the descriptions. The proposed language requires only 10~30% of the # of lines to describe the same functionality compared with RTL VHDL.
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FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.
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This paper proposes an area-efficient FIR filter architecture for sampling rate conversion of hi-fi audio data. Sampling rate conversion(SRC) block converts audio data sampled at 96KHz down to 48KHz sampled data and vice versa. 63-tap FIR filter coefficients have been synthesized that gives 100dB stop band attenuation and 5.2KHz transition bandwidth. Time-shared filter architecture requires only one multiplier and accumulator for 63-tap filter operation. This results in huge hardware saving of up to 10~19 times smaller compared with traditional FIR structure.
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본 논문에서 기술하고 있는 디블로킹 필터는 ISO/1EC 14496-2 의 디블로킹 필터링 알고리즘[1][2]을 기반으로 한다. 한 개의 레지스터 뱅크를 이용한 효율적인 데이터 스케줄링을 통해 면적과 전력 측면에서 디블로킹 필터를 사용함으로써 생기는 오버헤드를 최소화 시켰으며, CIF 급 영상을 27MHz 동작주파수에서 실시간으로 처리할 수 있도록 설계 하였다. 0.25㎛ Standard Cell Library 로 합성한 결과 총 9800 게이트로 구성 되었으며, 외부 메모리의 도움 없이 동작 시키기 위해 4.4KByte의 버퍼가 사용되었다.
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본 논문에서는 현재 MPEG, JPEG 압축 알고리즘에서 쓰이는 DCT(Discrete Cosine Transform)기반의 손실 영상 압축에 사용되는 양자화(Quantization) 처리에 필요한 나눗셈 연산기를 제안한다. 영상 데이터 처리를 위한 양자화기(Quantizer)는 DCT로부터 매 사이클마다 영상 데이터를 입력 받아 양자화 처리를 해야하며 보다 나은 영상 데이터를 위해 최종 나눗셈 결과 즉, 몫을 소수 첫째자리에서 반올림(Rounding)해야 한다. 이를 위해 반올림 동작이 추가된 Pipelined Nonrestoring Array Divider를 설계하였다. 제안된 방법의 타당성을 검증하기 위해 DCT로부터 나온 영상 데이터를 제안된 구조의 양자화기로 양자화하여 일반 양자화기에서 나온 압축된 데이터와 비교해 보았다. 또한 합성기(Synthesis)를 통하여 실제 하드웨어 크기를 분석하였다.
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본 논문에서는 MPEG-4 디블록킹 필터를 매크로블록 단위의 효율적인 파이프라인 구조를 사용하여 구현하였다. MPEG-4 QCIF/CIF 영상 시퀀스의 디블록킹 필터링 효과를 보일것이며, 디블록킹 필터링의 많은 계산량을 줄임과 동시에 낮은 클록에서 실시간 처리할 수 있는 구조를 제안하였다. 대부분 블록기반의 비디오 코딩 시스템에서, 블록 에지 효과는 블록기반 영상 압축에 치명적인 화질 저하를 나타낸다. 특히 압축 비율이 커질수록 화질 저하는 뚜렷하다. 그래서, 영상 후처리 기술로서 디블록킹 필터를 사용하여 블록 에지 영향을 줄임으로써 영상 화질을 향상시킨다. 그러나 디블록킹 필터의 주요 단점은 많은 계산량을 요구하고 있어서 구현에 어려움이 있다. 이 문제를 해결하기 위해, MPEG-4 디블록킹 필터를 매크로 블록단위의 파이프라인 구조로 설계하였고, 실시간으로 동작하는 MPEG-4 SP@L2의 비디오 코덱 칩을 구현하였다.
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In this paper, we have analyzed algorithm of physical layer, data link layer and MAC layer of Out-Of-Band (OOB) specified in the OpenCabl
$e^{TM}$ SCTE-55-2 2002$^{[3]}$ and designed architecture of the OOB processor. The OOB processor performs fundamental multiple access control for the OOB channel and extracts session key information from a EMM packet for descrambling MPEG-2 streams. In this paper, we have implemented a prototype board for the DVS167 OOB processor and verified it.t. -
An Eye Ball Sensor (EBS) is a system that locates the point where the user gazes on. The conventional EBS using a CCD camera needs many peripherals, software computation causing high cost and power consumption. This paper proposes a compact EBS using smart CMOS Image Sensor (CIS) pixels. The proposed single chip EBS does not need any peripheral and operates at higher speed and lower cost than the conventional EBS. The test chip was designed and fabricated for 32
$\times$ 32 smart CIS pixel array with a 0.35 um CMOS process occupying 5.3$\textrm{mm}^2$ silicon area. -
The low power motion estimation for MPEG-4 is a soft-core for hardwired motion estimation block in MPEG-4. This motion estimation is modified by 10 difference mode. So, this motion estimation decrease a power consumption compare conventional step search. This modified 4SS Low power Motion Estimation has been tested and verified to be valid for implementation of FPGA. The average PSNR between the original image and the motion-compensated image is 28.25dB. And Power consumption is 26mW.
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TCP/IP 를 포함하는 데이터 네트워킹 프로토콜을 구현함에 있어, 기존에는 소프트웨어 방식으로 구현되었던 모듈들을 하드웨어로 구현하는 프로젝트를 수행하면서, CPU 와 하드웨어 모듈과의 통신을 중계하는 모듈을 구현하였다. 본 논문에서는 TCP/IP 하드웨어와 CPU 와의 통신을 위한 Host Interface 의 기능에 대해 다루고 구현 방식을 Control flow와 Data flow의 입장에서 설명하였다. 우선, Host Interface 의 기능을 설명하고 Host Interface 의 입출력 신호를 정의하였다. Host Interface에서 이루어지는 CPU와 하드웨어 모듈간의 통신을 제어정보 흐름과 데이터정보 흐름으로 나누고 제어흐름을 위해서는 Command/Status Register 를 두었고, 데이터 흐름을 위해서는 CPU와 데이터 RAM 사이에 FIFO 를 두어 데이터의 흐름이 신속히 이루어지도록 하였다. 끝으로 Host Interface 와 주변 모듈들간의 통신에 대한 Testcases에 대해서도 다루었다.
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This paper proposes an emulation environment for SoC designs using small number of large gate-count FPGA's and a PC system. To overcome the pin limitation problem in partitioning the design when the design size overwhelms the FPGA gate count, we use bus splitter modules that replicate on-chip bus signals in one FPGA to arbitrary number of other FPGA's with minimal pin count. The proposed scheme is applied to the emulation of 2 million gate multimedia processing chip using two Xilinx Viretex-2 6000 FPGA devices in 6.6MHz operating frequency. An ARM core, memories, camera and LCD display are modeled in software using dual 2GHz Pentium-III processors. This scheme can be utilized for more than 2 FPGA's in the same ways as two FPGA case without losing emulation speed.
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Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-
${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells. -
본 논문은 멀티미디어 데이터 처리를 위한 효율적인 RISC 프로세서 유닛의 설계를 목표로 Vector 프로세서의 SIMD(Single Instruction Multiple Data) 개념을 바탕으로 고정된 연산기 데이터 비트 수에 비해 상대적으로 작은 비트수의 데이터 연산의 부분 병렬화를 통하여 멀티미디어 데이터 연산의 기본이 되는 곱셈누적(MAC : Multiply and Accumulate) 연산의 성능을 향상 시킨다. 또한 기존의 MMX나 VIS 등과 같은 범용 프로세서들의 부분 병렬화를 위해 전 처리 과정의 필요충분조건인 데이터의 연속성을 위해 서로 다른 길이의 데이터 흑은 비트 수가 작은 멀티미디어의 데이터를 하나의 데이터로 재처리 하는 재정렬 혹은 Packing/Unpacking 과정이 성능 전체적인 성능 저하에 작용하게 되므로 본 논문에서는 기존의 프로세서의 연산기 구조를 재이용하여 병렬 곱셈을 위한 연산기 구조를 구현하고 이를 위한 데이터 정렬 연산 구조를 제안한다.
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본 논문에서는 디지털 데이터 내에 사용자의 정보나 저작권 정보를 나타내기 위해 삽입되는 워터마크를 추출할 때 원본 이미지나 개인 키를 필요로 하지 않는 Blind Watermarking 방법을 개선하였다. 기존의 워터마킹 방법에서는 워터마크를 추출하기 위해 원본 이미지를 사용하거나 원본 이미지를 사용하지 않는 경우에는 개인 키를 사용하여 워터마크를 추출하였다. 제안하는 워터마킹 알고리즘은 워터마크를 주파수 대역 별로 삽입하는 것으로써 수정된 DCT 계수를 기반으로 하였고, 삽입 및 추출 연산의 복잡성을 배제하여 속도가 빠르고 하드웨어의 구조가 간단하다. 또한, 워터마크를 저 주파수 대역과 고 주파수 대역에 삽입하여 압축 및 에러 환경에 강인한 성격을 가진다. 제안한 알고리즘의 FPGA와 PCI Interface 를 통한 구현 및 검증에 대해서도 논하였다.
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Differential Power Analysis(DPA) is powerful attack method for smart card. Self-timed circuit has several advantages resisting to DPA. In that reason, DPA countermeasure using self-timed circuit is thought as one of good solution for DPA prevention. In this paper, we examine what self-timed features are good against DPA, and how much we can get benefit from it. Also we test several self-timed circuit implementation style in order to compare DPA resistance factor. Simulation results show that self-timed circuit is more resistant to DPA than conventional synchronous circuit, and can be used for designing cryptographic hardware for smart-card.
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본 논문에서는 Lifting-Based Scheme을 이용한 DWT(Discrete Wavelet Transform) 의 개선된 행 처리기의 구조를 제안 하였다. 제안된 행 처리기는 3개의 Adder 와 2개의 shifter를 사용 하였고 dual-port RAM을 사용하여 파이프 라인 구조를 취하여 각 클럭마다 열처리기에서 사용할 데이터를 발생 한다. 이러한 행 처리기의 파이프 라인 구조를 개선하여 Adder를 줄이고 행 처리기의 이용률을 최대로 하여 하드웨어의 공간적 비용 절감 효과를 가져 왔다. 제안된 구조는 Verilog를 사용하여 RTL설계를 한뒤 시뮬레이션으로 그 동작을 확인 하였다.
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High Speed data transmission over a long length of cable is limited due to the limited bandwidth of a cable which introduces ISI(Inter Symbol Interference). In order to compensate for the loss and phase dispersion in the cable, a pulse shaping in a transmitter and a line equalizer in receiver can be used. This paper presents a low-power and small-ana analog adaptive pulse shaping circuit and line equalizer, The design was fabricated in a 0.25
${\mu}{\textrm}{m}$ mixed-signal CMOS process. The proposed pulse shaping circuit and equalizer operate at 400Mb/s on 50m STP(Shielded Twisted Pair) cable. It consumes 28.5${\mu}{\textrm}{m}$ with a 2.5-V power supply and occupies only 0.098$\textrm{mm}^2$ . -
본 논문에서는 3-상 클럭을 이용하여 UP/DOWN 변환을 동시에 수행하는 DC/DC 변환기의 설계에 대해 설명한다. 기존의 UP/DOWN DC/DC 변환기의 경우에는 한 스텝당 변화하는 전압의 양이 많아서 출력에 수십 mV의 리플이 존재하게 된다. 이 리플을 줄이기 위해서는 L, C의 값을 크게 해 주어야하는 문제가 있다. 그러나, 설계된 UP/DOWN DC/DC 변환기는 기존의 UP/DOWN DC/DC 변환기의 구조를 가지면서, 3-상 클럭을 이용하여 한 스텝당 변화하는 전압의 양을 작게 하여 작은 L, C의 값을 가지고도 4mV이하의 출력 리플을 갖는 안정된 전압 변환을 하도록 설계하였다. 설계된 변환기는 0.25㎛ standard CMOS 공정을 이용하여 구현하였다. 구현 된 칩의 면적은 1.8 mm × 0.8 mm이다.
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본 논문에서는 휴대폰에 사용하는 리튬-이론 배터리(Li-Ion battery)를 충전하기 위한 충전 IC 의 설계에 대해서 기술한다. 정전류(Constant Current)/ 정전압 (Constant Voltage) 방식을 이용하여 리튬-이론 배터리를 충전을 하였다. 이 충전 과정을 제어하기 위해서 일반적으로 사용되는 ADC, DAC 와 MICOM 을 사용하지 않고, hardwired control logic 을 이용하여 적은 면적을 가지고도 기존의 충전 과정을 수행하도록 하였다. 충전 IC 외부에 사용되는 저항들을 내부에 집적하여 사용하는 부품의 수를 현저히 줄였다. 충전기와 리튬-이온 배터리를 연결하는 선(wire)로 저항에 의한 전압강하(voltage drop)를 외부에서 보상할 수 있도록하여 리튬-이온 배터리가 가장 안정적인 전압인 4.2 V로 충전 될 수 있도록 하였다. 외부 온도 검사 블록에서 저항을 이용한 전압 분배를 사용하지 않고, 정전류원을 이용하여 외부 온도 변화를 측정할 수 있도록 하였다. 리튬-이온 배터가 전정류와 정전압으로 4.2 V로 충전 되었으며, 충전 IC 의 소비 전력은 37 mW(analog part)이다. 충전 IC는 0.6 ㎛ standard CMOS 공정을 이용하여 설계하였다.
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Chip Pin Parasitic은 실제 Chip Pad에서부터 Bonding Wire를 통한 Package Lead Frame까지를 의미한다. 여기서, Lead Frame 및 Bonding Wire에서 Inductance 및 작은 저항이 보이고, Chip Pad에서의 Capacitance, 그리고 Pad 부터 Ground까지의 Return Path에서 발생하는 저항이 보인다. 이들을 모두 합하면 L, R, C의 Series로 나타낼 수 있다. 본 논문에서는 이런 Chip Pin Parasitic을 추출 하기 위해서 TDR(Time Domain Reflectometer)과 NA(Network Analyzer)를 사용하였는데, TDR의 경우 PCB를 제작하여 Chip을 Board위에 붙인 후 Time Domain에서 측정 하였고 NA의 경우 Pico Probe를 이용하여 Chip pin에 직접 Probing해서 Smith Chart를 통하여 Extraction 값을 추출했다. 이 경우, NA를 이용한 측정이 좀 더 정확한 Parasitic 값을 추출할 수 있으리라 예상되겠지만, 실제로 Chip이 구동하기 위해서는 Board위에 있을 때의 상황도 고려해야 하기 때문에 TDR 추출 값과 NA 추출 값을 모두 비교하였다.
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In this paper, we proposed high slew-rate and low-power OP-AMP of the data driver for TFT-LCDs. Proposed OP-AMP contains newly developed rail-to-rail class-AB input circuit which enables the low-quiescent current and high slew-rate OP-AMP. The slew-rate and the quiescent current of the proposed OP-AMP are 31.2V/
$\mu$ sec and 5$\mu$ A, respectively. -
We have developed Logic Design Training Kit for studying, actual training, designing of FPGA(Xillinx) or CPLD(ALTERA CPLD), the Digital Logic Device. This training kit has 12 matrix keys, RS232 port for serial communication and uses LED array. six FND(Dynamic), LCD as display part. That is standard specification for digital logic training kit. Special point of this kit is that we make two logic device trainig kit. This two logic device kit have more smaller and simple architecture because only uses one chip. That chip already includes a lot of functions that need for training kit, such as : complex logic circuit needed the two kind of logic devices, 16 way of system clock deviding function, serial communication interrupt....etc. We called that one chip is Center Bridge Chipset ; Xillinx FPGA Spartan2. User can select between using one device of FPGA or CPLD, or uses both them. Because of, Center Bridge Chipset has profitable architecture. it can work as Logic Device's networking with Master-Slave connection When using both logic devices.
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A logic design training kit with print port emulation function was developed. The input device of the kit was 4
$\times$ 4 key input and 6 FND(DYNAMIC) and LCD were used as out put devices and the output device were also can controlled by PC connectde by print port to the kit. The emulator was coded by Visual Programming C++(MFC) -
본 논문에서는 높은 슬루율을 가지고 전압편차 (offset)보상 기능을 가지면서도 전력소모가 적은 고계조 TFT-LCD 데이터 드라이버 구동용 단일이득 연산증폭기(unit gain op-amp)의 바이어스 회로 및 구동 방법을 제안하였다. 제안한 단일이득 연산증폭기는 일반적으로 사용되고 있는 전압편차 보상기능을 가진 단일이득 연산증폭기에 adaptive bias기능을 추가한 것으로써, 기존 구조에 비해 50%이상의 소비 전력 절감 효율을 보였다.
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This paper presents a novel low power driving circuit for passive matrix organic lighting emitting diodes (OLED) displays. The proposed driving method for a low power OLED driving circuit which reduce large parasitic capacitance in OLED panel only use current driving method, instead of mixed mode driving method which uses voltage pre-charge technique. The driving circuit is implemented to one chip using 0.35
${\mu}{\textrm}{m}$ CMOS process with 18V high voltage devices and it is applicable to 96(R.G.B)X64, 65K color OLED displays for mobile phone application. The maximum switching power dissipation of driving power dissipation is 5.7mW and it is 4% of that of the conventional driving circuit. -
This paper presents a novel low voltage reference circuit under the MOS threshold voltage(V
$_{th}$ ) in standard CMOS process. It is based on the weighted difference of the gate-source voltages of an NMOS and a PMOS operating in saturation region. The voltage reference is designed for low power OLED driver ICs. The proposed circuit is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology. The minimum supply voltage is 2V, and the typical temperature coefficient is 99.6ppm/ C.C. -
In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.
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DWT(Discrete Wavelet Transform)를 2차원 하드웨어로 구현하기 위해서 많은 하드웨어와 실행시간이 들기 때문에 효율적인 구조가 중요하다. 그래서, 이 논문에서는 2차원 DWT에 대한 효율적인 하드웨어 이용률과 크기의 감소, 완벽한 레지스터 이용률, 규칙적인 데이터 흐름으로 필터 길이의 확장을 쉽게 할 수 있도록 구조를 개선하고, 개선된 구조를 VHDL로 검증하였다.
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The performance of elliptic curve based on public key cryptosystems is mainly appointed by the efficiency of the underlying finite field arithmetic. This work describes a finite field multiplier and divider which is implemented using SystemC. Also this present an efficient hardware for performing the elliptic curve point multiplication using the polynomial basis representation. In order to improve the speed of the multiplier with as a little extra hardware as possible, adopted hybrid finite field multiplication and finite field divider.
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Design verification problem is emerging as an important issue to detect any design errors at the early stage of the design. Conventionally, design verifications have been done using a simulation technique. However, this technique has been proved not to cover all potential design errors. Therefore, formal technique is often used to verify digital circuits as an alternative. In this paper we adopted formal verification technique and verified some important properties derived from our pipelined digital systems, using SMV (Symbolic Model Verifier). Our example shows that model checking method (one of formal verification techniques) can be effectively performed in verifying the large digital systems.
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This paper proposes new SPICE Macro-Model of MTJ(Magnetic Tunnel Junction). This Macro-Model has five I/O terminals, reproduces MR characteristics including hysteresis and behaves correctly to time varying input signals. Furthermore, this Model can be easily modified to various MTJs with different characteristics by simply varying internal parameters.
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본 논문에서는 고속 적외선 무선 데이터통신(IrDA) 에 사용되는 트랜스임피던스 증폭기(Transimpedance Amplifier)를 설계하였다. 트랜스임피던스 증폭기는 잡음을 최소화하기 위해 PMOS 차동 구조로 설계하였으며 입력과 출력의 피드백을 통해 주위의 빛에 의해 발생되는 photocurrent 에 의한 DC 옵셋을 제거하였다 또한 공통 게이트(CG)와 Regulated Cascode Circuit (RGC)을 추가하여 대역폭(Bandwidth)을 향상시켰다. 설계한 회로는 0.25 um CMOS 공정을 이용하였으며 트랜스임피던스 이득은 200 MHz의 대역폭에서 10 KΩ (80 dBΩ )이다. 전체 전력 소비는 18 mW이다.
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본 논문에서는 고속. 저전력에 적합한 개방 구조를 갖는 8-비트 500Msmaples/s 2-Step ADC 를 제안하였다. 500Msmaples/s 의 고속 동작을 위해서 기존의 M-DAC을 이용한 폐쇄 구조 대신 개방형 구조를 사용하였다. 이와 더불어 저전력을 구현하기 위해서 analog-latch 를 제안하여 동적 동작을 수행시킴으로써 전력 소모를 줄였으며 , mux 의 구현 시 reset switch를 이용하여 로딩 시간을 개선함으로써 high-speed 에 적합하도록 설계하였다. 제안된 ADC 는 1-poly 6-metal 0.18um CMOS 공정을 이용하였으며 1.8V 전원 전압을 이용하여 250mW 의 전력을 소모하며 500M 샘플링 주파수에서 120MHz 신호 입력 시 7.6 비트의 ENOB를 얻을 수 있었다.
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본 논문에서는 개방형 파이프라인 구조를 이용한 8비트 500Msamples/s ADC를 제안하였다. 8-비트의 해상도에 적합하면서 전력 소모가 적은 5 단 파이프라인 구조로 설계하였으며, 고속 동작에 적합하게 MUX 스위치에서 선택한 신호를 인터폴레이션하는 개방형 구조를 채택하였다. 전력 소모와 전체 칩 면적을 줄이기 위해서, 각 단에서 필요한 신호의 수를 줄이도록 설계하였다. 설계된 ADC 는 3 개의 신호를 이용하여 구현 함으로서 각 단에서의 증폭기 수틀 줄일 수 있었다. 또한 1.8V 의 낮은 전원 전압에 의한 작은 입력 범위에서 8-비트의 해상도를 만족하기 위해서 Offset Cancellation 기법을 사용하였다. 제안된 ADC 는 0.18μ m 일반 CMOS 공정을 이용하여 설계되었으며 시뮬레이션 결과 500Msamples/s에서 220mW의 전력 소모를 가지며, 1.2Vp-p (Differential) 입력 범위에 대해서 약 48dB의 SNDR을(8-비트의 해상도) 가짐을 확인할 수 있었다.
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At the processing capabilities and operating frequency of embedded system are growing, so is the needed data bandwidth to fully utilize the processing capability. The ability to transfer huge amount of data between the embedded core and external devices is required for efficient system operation. In this paper, the data communication architecture for the mixed-clock system is proposed. The dynamic priority adaptation algorithm for bus arbitration is proposed for bandwidth guarantee. The communication architecture that incorporates the proposed arbitration algorithm adapts the priority of communication components dynamically based on the information from FIFO. The experiments show that the measured bandwidth of each component traces the required bandwidth well compared to the other arbitration algorithms
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This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-
${\mu}{\textrm}{m}$ CMOS process. -
A new adder-and-accumulator (A
$^2$ C) adapted to pipelined Δ$\Sigma$ modulators is proposed in this paper. With the viewpoint of area consumption, registers are removed in the existing pipelined Δ$\Sigma$ modulator, and then adder and accumulator are merged. In order to optimize area consumption, speed and power consumption, dynamic carry look-ahead adder (CLA) is adopted in$A^2$ C. Moreover, a guideline for the transistor sizing in CLA with regard to the minimization of the energy-delay-area product (EDAP) is proposed[1]. The proposed$A^2$ C has been verified by HSPICE simulations. -
본 논문은 DI(delay insensitive) 지연 모델을 적용한 비동기 회로의 데이터 전송시 발생되는 신호 천이의 수를 감소시키기 위한 새로운 데이터 인코딩 기법과 신호 천이 방법을 제시한다. DI 지연 모델을 적용한 비동기 시스템은 배선 지연에 관계없이 동작이 필요한 모듈에만 데이터와 핸드쉐이크를 위한 이벤트 신호를 전송하는 장점을 갖는다. 그러나 신호의 유효성과 동작 완료 검출을 위해 듀얼레일 데이터 인코딩이 필요하며 이는 비동기 회로의 크기를 증가시키고 이로 인해 전력 소비가 증가한다. 전력 소비를 감소시키기 위해 신호 천이의 수를 줄여야 하며, 본 논문에서는 제안한 신호 천이 기법을 적용하여 실험적으로 약 21%의 전력 소비 감소 결과를 얻었다.
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본 논문에서는 비디오 신호 인터페이스를 위해 10비트 50MHz ADC 를 설계하였으며 DCL(digital-error correction logic)을 갖는 3-3-3-4 구조의 파이프라인 방식을 사용하였다. SHA(sample and hold amplifier)와 MDAC (multiplying digital-to-analog converter)에 쓰이는 증폭기는 높은 이득을 갖도록 gain-boosting 기법을 적용하였으며, 전력소모와 면적을 줄이기 위해 capacitor scaling 기법을 적용하였다. 본 ADC 는 0.35 μm double-poly four-metal n-well CMOS 공정으로 설계 및 제작하였으며, 전체 회로는 3.3V 단일 전원 전압에서 동작하도록 설계하였다. 측정 결과 5MHz 의 입력을 인가하였을 때 SNDR 은 56.7dB, 전체 전력 소모는 112mW 이며, 입출력 단의 패드를 포함한 전체 칩 면적은 2.6mm×2.6mm이다.
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Due to the differential transmission technique and low voltage swing, LVDS has been widely used for high speed transmission with low power consumption. This paper presents the design and implementation of interface circuits for 1.5Gb/s operation in 0.35um CMOS technology. The interface circuit ate fully compatible with the low-voltage differential signaling(LVDS) standard. The LVDS proposed in this paper utilizes a sense amplifiers instead of the conventional differential pre-amplifier, which provides a 1.5Gb/s transmission speed with further reduced driver output voltage. Furthermore, the reduced driver output voltage results in reducing the power consumption.
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This paper describes a 2.5V 80dB 360MHz CMOS VGA. A new variable degeneration resistor is proposed where the dc voltage drop over the degeneration resistor is minimized and employed in designing a low-voltage and high-speed CMOS VGA. HSPICE simulation results using a 0.25
${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than 1.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$ $\times$ 360${\mu}{\textrm}{m}$ . -
This paper presents a cross-coupled RF VCO with high-Q MEMS-based spiral inductors. Since the use of high-Q inductors is critical to VCO design, MEMS-based spiral inductors with the Q-factor of nearly 22 are used for the RF VCO with an active cascode current source. The RF VCO circuits including spiral inductors have been designed and simulated in GaAs MMIC-MEMS process. The simulation results of the VCO circuits showed the phase noise of -180dBc/Hz at an offset frequency of 500KHz. The RF VCO circuit simulatinon used 2mA DC current and 3.3V supply.
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본 논문에서는 수용성 포토레지스트를 이용하여 기존의 패턴 형성 방법을 대신하여 유기 활성층을 리소그라피을 할 수 있도록 하였으며 스핀코팅 방법을 사용하여 대면적 리소그라피를 가능하게 하고 포토 마스크를 사용하여 매우 작은 선폭의 패턴을 형성할 수 있도록 하였다. 그리고 이러한 방법을 이용하여 트랜지스터를 제작하였고 기존의 방법으로 제작한 트랜지스터의 특성과 비교를 해보았다.
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This paper reports the correlation between dielectric constant and degree of amorphism of the hybrid type Si-O-C thin films. Si-O-C thin films were deposited by high density plasma chemical vapor deposition using bistrimethyl- silylmethane(BTMSM,
$H_{9}$ C$_3$ -Si-C$H_2$ -Si-C$_3$ $H_{9}$ ) and oxygen precursors with various flow rate ratio. As-deposited film and annealed films at 40$0^{\circ}C$ were analyzed by XRD. The Si-O-C thin films were amorphous from XRD patterns. For quantitative analysis, the diffraction pattern of the samples was transformed to radial distribution function by Fourier analysis, and then compared with each other. The degree of amorphism of annealed films was higher than that of as-deposited ones. The dielectric constant varied in accordance with flow rate ratio of precursors. The lowest dielectric constant was obtained from the as-deposited film which has the highest degree of amorphism after annealing. -
In this study, the white organic light emitting device was fabricated using ITO/a-NPD:DCM/a-NPD/BCP/Alq3/Al structure. Blue emission by a-NPD and orange emission by energy transfer between a-NPD and DCM embodied the white emission. The optimal structure of the white OLED is ITO/a-NPD:DCM(50
$\square$ )/a-NPD(150$\AA$ )/BCP(100$\square$ )/Alq$_3$ (200$\square$ )/Al. We varied the doping concentration of DCM properly and obtained high purity white emitting light. The CIE coordinate and maximum luminance of the devices was obtained (0.310, 0.333) and 400cd/$m^2$ at 11Volt. -
본 논문에서는 sub-micron 소자에서 SCE(Short Channel Effect) 억제를 위한 Halo 와 SSR(Super Steep Retrograde Well) 적용에 따른 analog 특성의 열화를 석하고 이를 개선하기 위해 Twist 이온주입과 In, Sb Halo 를 채택하였다. Analog 특성은 CMOS 의 amplifier 과 Comparator 로의 사용을 고려해 Drain Rout과 Early voltage를 이용해 나타내었으며 Digital 성능을 함께 고려하였다. 실험결과 NMOS 의 경우 45 twist Halo 조건에서, PMOS의 경우 As보다 Sb를 Halo 로 적용하는 경우 더 우수한 analog 특성을 나타내었다.
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This paper presents in-circuit system-on-chip verification and debugging environment. To maximize the emulation speed, the software part is compiled natively for the host computer and the hardware part is mapped into FPGA. The two parts communicate with each other in transaction level. The operation of the hardware part and the software part is recorded independently during the emulation, and after the emulation is over, they are merged in a waveform to give user a unified view that covers both hardware and software.
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We proposed a new two-stage operational amplifier that increases the slew rate by adding some simple circuitry to the conventional structure. The proposed circuit is simulated by HSPICE and the slew rate of the proposed circuit is improved more than 10 times than that of conventional one in slewing state without considerable increments in area and power consumption.
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As increasing the size and complexity of hard-ware and software system, more efficient design methodology has been developed. Especially design-reuse technique enables fast system development via integrating existing hardware and software. For this technique available hardware/software should be prepared as component-based parts, adaptable to various systems. This paper introduces a component-based VHDL analyzer allowing to be embedded in other applications, such as simulator, synthesis tool, or smart editor. VHDL analyzer parses VHDL description input, and performs lexical, syntactic, semantic checking, and finally generates intermediate-form data as the result. VHDL has full-features of object-oriented language such as data abstraction, inheritance, and polymorphism. To support these features special analysis algorithm and intermediate form is required. This paper summarizes practical issues on implementing high-performance/quality VHDL analyzer and provides its solution that is based on the intensive experience of VHDL analyzer development.
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This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.
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An electronic ballast for driving automotive HID lamps is presented. The circuit topology is composed of a fly back converter, a Ful bridge inverter, and an igniter. A prototype was developed and tested on a 35W lamp with a 12V input voltage. To avoiding the acoustic resonance, the full bridge inverter is operated at 250Hz and provided a squared-wave voltage source to the lamp. The transient and steady state characteristics of the tested HID lamps are measured and analyzed.
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In this paper, we designed GF(2
$^{m}$ ) inversion and division processor for Elliptic Curve Cryptographic system. The processor that has 191 by m value designed using Modified Euclid Algorithm. The processor is designed using 0.35${\mu}{\textrm}{m}$ CMOS technology and consists of about 14,000 gates and consumes 370 mW. From timing simulation results, it is verified that the processor can operate under 367 Mhz clock frequency due to 2.72 ns critical path delay. Therefore, the designed processor can be applied to Elliptic Curve Cryptographic system. -
In this paper, Si anisotropic etching characteristics of tetramethylammonium hydroxide (TMAH)/ ammonium persulfate (AP) solutions were investigated to realize the optimum structure of a diaphragm for the piezoresistive pressure sensor application. Due to its low toxicity and its high compatibility with the CMOS processing, TMAH was used as Si anisotropic etchants. The variations of Si etch rate on the etching temperature, TMAH concentration, and etching time were obtained. With increasing the etching temperature and decreasing TMAH concentrations, the Si etch rate is increased while a significant non-uniformity exists on the etched surface because of formation of hillocks on the <100> surface. With the addition of AP to TMAH solution, the Si etch rate is increased and an improvement in flatness on the etching front is observed. The Si etch rate is also maximized with increasing the number of addition of AP to TMAH solution per one hour. The Si square diaphragms of 20
${\mu}{\textrm}{m}$ thickness and 100~400${\mu}{\textrm}{m}$ one-side length were fabricated successfully by applying optimum Si etching conditions of TMAH/AP solutions. -
본 논문에서는 microcolumn 을 위한 초소형 전자빔 deflector 의 제작방법과 microcolumn array 에서 deflector 의 외부 패드를 최소화 할 수 있는 새로운 배선방법을 기술하였다. 배선의 통로 및 절연체 역할을 하는 Pyrex glass 의 양쪽에 각각 실리콘 웨이퍼의 양극접합 및 deep reactive ion etching(DRIE)과 금속 전기 도금을 이용하여 다층배선을 하였다. 이 배선방법을 이용하면 microcolumn array 가 수백개가 되더라도 deflector 의 외부 패드는 항상 8개를 유지할 수 있다.
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In this paper, a new CMOS fully integrated frequency-to-digital converter is proposed. The operation of the proposed circuit is based on a pulse-shrinking delay element. In the proposed circuit, a resolution of the converted digital output can be easily improved by increasing the number of the pulse-shrinking element. Also the input frequency range can be easily changed through controlling bias voltage in the pulse-shrinking element. The simulation of the designed circuit carried out by HSPICE using the CMOS 0.35
${\mu}{\textrm}{m}$ process technology. -
In this paper, we studied plasma damage of MIS capacitor with
$Al_2$ O$_3$ dielectric film. Using capacitor pattern with the same area but different perimeters, we tried to separate etching damage mechanism and to optimize the dry etching process. After etching both metal and dielectric layer by the same condition, leakage current and C-V measurements were carried out for Pt/A1$_2$ O$_3$ /Si structures. The flatband voltage shift was appeared in the C-V plot, and it was caused by the variation of the fixed interface charge and the interface trapped charge. From I-V measurement, it was found the leakage current along the periphery could not be ignored. Finally, we established the process condition of RF power 300W, 100mTorr, Ar/Cl$_2$ gas 60sccm as an optimal etching condition. -
This study shows the change of the structural characteristic of AIN thin film deposition with the change of the deposition conditions such as Ar/
$N_2$ gas ratio, operating pressure in chamber, and the distance between substrate and target in RF Magnetron Sputtering. The orientation and surface roughness of AIN thin film are studied by using XRD and AFM and the thickness is measured by using STYLUS PROFILER. While we can not identify the orientation of the thin film deposited in Ar only, we can obtain the (100) orientation of the thin film with the addition of$N_2$ to Ar. Especially the thin film deposited at 10% of Ar/$N_2$ gas ratio appears to be the most (100) oriented. The (100) orientation of thin film becomes weaker as the operating pressure becomes higher. The further distance between substrate and target is stronger the (100) orientation of the thin film is. The (100) orientation becomes weaker and (002) orientation starts to appear as the distance is shorter. -
A distortion suppression technology for employing multiple inputs in 3n+1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of inputs in current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to sum of parasitic capacitance in input terminals, to the derivative of the output signal and also to the inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation.
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This paper is about the optimized fabricated parameter in the EDMOSFET(Extended drain MOSFET) with a various temperature. As we know, the two important factors of EDMOSFET parameters are breakdown voltage and on Resistance. So, we have aims of the power EDMOSFET design to have high breakdown voltage and low on resistance. Thus in this paper, we will show the figure of merit in LDMOS (BV/Ron) in accordance with increase in temperature(300K-500K, step:50K), and measure electronic characteristics of power EDMOSFET. As a result, the important factors in design of EDMOS are temperature and Lg.
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In this paper, we deposited A1
$_2$ O$_3$ thin film using atomic layer deposition(ALD) method on Ti and fabricated metal-insulator-metal(MIM) capacitor. In the result of this study, the typical deposition rate was about 1.12$\AA$ /cycle. About 30 nm of Ti was consumed during deposition and TiO$_{x}$ was formed at the interface of A1$_2$ O$_3$ and Ti. Its surface roughness was 1.54nm. The leakage current density was 1.5 nA/$\textrm{cm}^2$ . The temperature coefficient of capacitance(TCC) of MIM capacitor was 41 ppm/$^{\circ}C$ at 1MHz and 100 ppm/$^{\circ}C$ at 100 kHz.z. -
For the first time, high quality ultra-thin strained Si/SiGe on Insulator (SGOI) substrate with total SGOI thickness(
$T_{Si}$ +$T_{SiGe}$ ) of 13 nm is developed to combine the device benefits of strained silicon and SOI. In the case of 6- 10 nm-thick top silicon, 100-110 %$I_{d,sat}$ and electron mobility increase are shown in long channel nFET devices. However, 20-30% reduction of$I_{d,sat}$ and electron mobility are observed with 3 nm top silicon for the same long channel device. These results clearly show that the FETs operates with higher performance due to the strain enhancement from the insertion of SiGe layer between the top silicon layer and the buried oxide(BOX) layer. The performance degradation of the extremely thin( 3 nm ) top Si device can be attributed to the scattering of the majority carriers at the interfaces. -
Germane-sillicide phase formation on S
$i_{0.25}$ G$e_{0.75}$ with Ni 100$\square$ , Co 10$\square$ /Ni 100$\square$ and Ni 50$\square$ /Co 10$\square$ /Ni 50$\square$ layer was studied by sheet resistance and Field Emission Scanning Electron Microscopy(FESEM). Thermal stability of nickel germane-silicide is found to be improved by sputtering Ni/Co/Ni on the SiGe. After annealing at 600, 650,$700^{\circ}C$ , 30min., the nickel germane-silicide formed by Ni 50$\square$ /Co 10$\square$ /Ni 50$\square$ layer achieved a sheet resistance less than 17ohms/sq.(almost the same to the value before furnace annealing for 30min.) , while the process of the other two ways result in high sheet resistance and even sheet resistance fail due to Ge segregation.ion. -
This paper shows the performance as a photodetector of InP/InGaAs HPT operated with a base bias and forntside optical injection through the emitter. InP/InGaAs HPT produced the high optical gain of about 16.2 where HPT is biased at Vc=1V, I
$_{B}$ =20$\mu$ A with an input optical power of 2.4$\mu$ W. And we examined that the optical gain of HPTs becomes larger when operating in 3-terminal configuration rather than 2-terminal with the floating base. The optical performance of InP/InGaAs HPT is an attractive to the PIN Photodetector for use in long wavelength optical receivers.s. -
This paper show the measured result of electrical characteristics of SOI-LDMOSFET that is one of the high voltage devises. Especially, we observed changes of breakdown voltage, threshold voltage, on-resistance, drain current, and transconductance in accordance with drift length, main parameter of LDMOSFET. Also, we achieved reliability analysis about device operation in high temperature environment because LDMOS is applied to smart power IC.
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본 논문에서는 OPVD시스템을 이용하여 펜타센 박막을 형성하였고 소자제작을 통해 그 특성을 평가 하였다. OPVD시스템을 이용하여 제작된 OTFT의 이동도는 0.01㎠/V·sec로써 기존의 OMBD로 제작된 OTFT보다 약 10배 정도 향상된 값을 나타냈으며, SS는 2.5Ion/off ratio 는 10⁴, 누설전류는 100pA 였다. 이러한 OPVD시스템에 의한 방법은 대면적 성막이 가능할 뿐 만 아니라 형성된 박막의 결정도 또한 기존의 OMBD방법으로 형성된 박막보다 월등하였다.
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In this work, we fabricated a gas-sensing device based on porous silicon(PS), and its I-V and C-V properties were investigated for sensing alcohol vapor. The structure of the sensor consists of thin Au/Oxidized porous silicon/porous silicon/Silicon/Al, where the silicon substrate is etched anisotropically to be prepared into a membrane shape. As the result, I-V curves showed typical tunneling property, and C-V curves were shaped like those of a MIS (metal-insulator- semiconductor) capacitor, where the capacitance in accumulation was increased with alcohol vapor concentration.
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This paper has been studied on wafer cleaning and photoresist striping in semiconductor fabrication processes using ozone solved deionized water. In this work, we have developed high concentration ozone generating system and high contact ratio ozone solving system to get high efficiency DIO
$_3$ . Through this study, we obtained 11% ozone gas concentration, 99.5% of ozone efficiency and 51% of solubility in deionized water. -
Lim, Gyu-Ho;Yu, Seong-Han;Heo, Jin-Seok;Kim, Kwang-Hyun;Jeon, Sung-Chae;Huh, Young;Kim, Young-Hee;Cho, Gyu-Seong 1093
본 논문에서는, CMOS APS Image Sensor 내에 포함되어 회로의 면적을 줄인 새롭게 제안된 CMOS Bandgap Reference Bias Generator (BGR)를 온도 및 방사능에 대한 응답을 실험하였다. 제안된 BGR 회로의 설계 목표는 V/sub DD/는 2.5V이상이고, V/sub ref/는 0.75V ± 0.5mV 마진을 가지게 하는 것이다. 제안된 BGR회로는 Level Shifter를 갖는 Differential OP-amp단과 Feedback-Loop를 가지는 Cascode Current Mirror를 사용하여 저전압에서도 동작을 가능하게 하였으며, 높은 출력저항 특성을 가지도록 하였다. 제안된 BGR회로는 하이닉스 0.18㎛ ( triple well two-poly five-metal ) CMOS 공정을 이용하여 Test Chip을 제작하였다. 온도의 변화와 Co-60 노출조건 하에서 Total ionization dose (TID) effect된 BGR회로의 V/sub ref/를 측정하여, 이를 평가하였다. 온도에 대한 반응은, 25℃ 일 때의 V/sub ref/에 대해, 각각 45 ℃에서 0.128%. 70℃에서 0.768% 변화하였다. 그리고 온도가 25℃일 때 50krad와 100krad의 방사능을 조사 하였을 경우, V/sub ref/는 각각 2.466%, 그리고 4.612% 변화하였다. -
Tunable thermo-optic filter for WDM system was designed and fabricated. The basic structure of the filter was a Fabry-Perot resonator and the center cavity layer was poly-Si. Quardraple layers of low and high refractive index materials were used as DBR mirrors. Tuning and transmission efficiencies was measured and compared with the simulation results. Tuning range of 9.4 nm can be obtained by 64.7
$^{\circ}C$ temperature changes and tuning efficiency was 0.144nm/K. The filter is to be assembled onto the micro optical bench with fiber optical path. -
In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.
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In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.
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본 연구는 switching mode 의 Power NMOSFET failure mode 에 관하여 분석하고 원인을 규명하였다. 분석된 power NMOSFET은 30V급이며, vender A의 상용화 제품이다. 발생한 failure mode는 power switch 회로에서 특정 ID 를 detect 하지 못하는 mode 였다. 측정결과 source voltage 가 저하되었으며, power NMOSFET DC 동작특성 분석 결과 Vgs 변화에 따라 Id 가 저하되었다. Fail 된 power MOSFET 특성값 reference는 동일 LOT의 양품을 선정하였다. De-cap후 Inversion 과 Accumulation mode 별로 Photoemission spectrum analyzer(PSA) 분석 방법을 적용하였다. 결과 accumulation mode 에서 intensity가 감소하였으며, forward diode mode에서 국소적으로 변화하는 영역이 검출되었다. SEM 분석결과 gate metal 과 source metal 의 micro-contact 이 이루어져 있었다. 이 경우 gate metal 과 source metal 사이 close loop 를 형성하여 gate charge량을 변화시켜 power NMOSFET의 출력을 저하하는 failure mode가 발생됨을 분석할 수 있었다.
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This review article gives a comprehensive compilation of recent developments in low temperature deposited poly Si flms, also known as microcrystalline silicon. The development of various ion energy suppression techniques for plasma enhanced chemical vapour deposition and ionless depositions such as HWCVD and expanding thermal plasma, and their effect on the material and solar cell efficiencies are described. A correlation between ef.ciency and the two most important process parameters, i.e., growth rate and process temperature is carried out. Finally, the application of these poly Si cells in multijunction cell structures and the best efficiencies worldwide by various deposition techniques are discussed.
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In this paper, a 1.5V CMOS high frequency operational amplifier for high frequency signal processing systems is presented. For obtaining the high gain and the high unity gain frequency with the 1.5V supply voltage, the op-amp is designed with simple two stages which are consisting of the rail-to-rail differential input stage and the class-AB output stage. The designed op-amp operates with the 1.5V supply voltage, and shows well the push-pull class-AB operation. The simulation results show the DC open loop gain of 77dB and the unity gain frequency of 100MHz for the 1㏁ ┃ 10pF load. When the resistive load R
$_1$ . is varied from 1㏁ to 1 ㏀, the DC open loop gain decreases by only 4dB. -
PZT(30/70) thick film was fabricated by using 1,3 propanediol-based sol-gel method. Prepared film of pyroelectric property was investigated by Dynamic method of modulation frequency dependence. Pyroelectric coefficient was obtained about 5.0
$\times$ 10$^{-8}$ C/$\textrm{cm}^2$ .K. The figure of merits for voltage responsivity and specific detectivity were 3.4$\times$ 10$^{-11}$ C.cm/J and 5.9$\times$ 10$^{-9}$ C.cm/J, respectively, because of relative high-dielectric constant and high-pyroelectric coefficient. Voltage responsivity was increased at low modulation frequency and it was decreased at high modulation frequency. Voltage responsivity was maximum 1.84 V/W at 10 Hz. As Johnson noise is dominant, Noise voltage was increased nearly proportional to f$^{-1}$ 2/. Noise equivalent power and specific detectivity were 2.83$\times$ 10$^{-7}$ W/Hz$^{1}$ 2/ and 3.13$\times$ 10$^{5}$ cm.Hz$^{1}$ 2//W the same frequency at 80 Hz, respectively. -
This paper presents the design method of a Colpitts type oscillator with coplanar waveguide(CPW) structures in the range of Ka-band frequency for transmitter and receiver modules. Series short stubs of CPW patterns provide inductances and capacitances in the range of Ka-band which can be expressed as a CLC-
$\pi$ equivalent circuit. The experimentation has employed ro4003 substrates as a CPW substrate which has a dielectric constant of 3.38 and a signal and ground space of 100um. A method of momentum simulation for the CPW patterns has performed with an ADS software tool of Hewlett-Packard Corp. Inductance and capacitance circuits of a Colpitts oscillator was interconnected to a MESFET with CPW bend structures of including the input and output impedance matching circuits of the active transistor. Circuit parameters for impedance matching were determined through the network conversion to the equivalent length of CPW transmission lines by using T-network 1$\pi$ -network conversion circuit. A Colpitts oscillator was fabricated on the substrate of a area of 8.5mm x 17.4mm with a MESFET of Fujitsu FMM5704X and CPW series short stubs. The design suggested the possibility of realizing oscillators on a planar surface for the wireless system of tansmitter and receiver modules in the frequency range of 30GHz -
본 논문에서는 위상/주파수 검출기을 설계시 문제가 되는 Reference Spur을 없게 하여 Low Noise를 구현할 수 있는 No Spike PFD(Phase Frequency Detector)를 제안한다. 위상동기루프의 특별한 형태로 차지 펌프 위상동기루프가 있다. 차지 펌프위상동기 루프는 일반적으로 3-state 위상/주파수 검출기를 이용한다. 이 3-state 위상/주파수 검출기는 기준 신호와 VCO 출력 신호의 위상차에 비례하는 디지털 파형으로 출력을 내보낸다. 차지 펌프 위상동기루프 그림 1 처럼 디지털 위상/주파수 검출기(PFD), 차지 펌프(CP), 루프 필터(LF), VCO로 구성된다. PFD 는 기준 신호와 VCO 에 의해 만들어진 출력 신호를 입력받아 각각의 위상과 주파수를 비교한다. 즉, 출력 신호가 기준 신호보다 느릴 때에는 출력 신호를 앞으로 당기기 위해서 up 신호를 넘겨주고, 출력 신호가 기준 신호보다 빠를 때에는 출력 신호를 뒤로 밀기 위해 down 신호를 넘겨준다. 차지 펌프(CP)의 전류를 Ip 라고 한다면, CP 에서 LF 로 흐르거나, LF에서 CP로 흐르는 전류 Ip의 평균량이 기준 신호와 VCO 출력 신호의 위상차에 비례하는 것이다.
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This paper has been studied about the implemention of the data-encription processor and imformation security system. Also in the paper, the brief contents of the verification of the data-encryption algorithm and the method of using HDL-level sources implemented is described. And then this paper has been designed for multi-level data secure system to verify and analyze the data-encryption processor implemented as VHDL.
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The area of the prototype device is less than 80mm
$^2$ . Operating with a 60ns clock cycle, the device typically dissipates only 300mW. The full functionality was proven by using the methodical test programs based on typical image processing operations. Also, we realized the whole process from conventional gray image to color image. Format converters, implemented using multidimensional access memories, transfer the data between the processing element array and conventional bit-parallel components in real time. The completed system is fully functional and performs typical low-level image processing tasks at speed exceeding 30 frames of traditional TV system per second. -
For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35
${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$ . -
SSN을 줄이기 위해 벌크단의 그라운드와 소스단의 그라운드를 분리한다. 이 방법을 사용하면 소스과 벌크의 전압 차이가 발생하는데 소스에 발생되는 전압은 기생인덕턴스로 인해 노이즈 전압이되고 벌크의 전압은 그라운드에 바로 연결되기 때문에 0V가 된다. 이 방법을 사용하면 소스단에 기생인덕턴스가 벌크단에 미치지 못하게 되어 노이즈를 줄일 수 있다.. 본 논문에서 나타난 결과는 공통그라운드를 사용한 구동 드라이버 보다 SSN을 10% 간단히 줄일수 있다.
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Now a days, many different kinds of display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED), and Liquid Crystal On Silicon (LCOS) are designed. And these display technologies will be used in many application products like High Definition Televisions (HDTVs) or mobile devices. In this paper, pattern generation circuit for display test is proposed. The proposed circuit will be embedded in the control circuit of display chip. Two differenct kinds of patterns is generated by the circuit. One is block pattern for color test, and the other is line pattern for pixel test. The shape of test pattern is determined by the values of registers in pattern generation circuit. The circuit is designed using Verilog HDL RTL code.
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In this paper, we present a reducing power consumption of a scheduling for module selection under the time constraint. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed scheduling of reducing power consumption is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our approach various HLS benchmark environment using chaining and multi-cycling in the scheduling techniques..
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We proposed a study on optimal clock period selection algorithm for low power RTL design. The proposed algorithm use the way of maintaining the throughput by reducing supply voltage after improve the system performance in order to minimize the power consumption. In this paper, it select the low power to use pipeline in the transformation of architecture. Also, the algorithm is important the clock period selection in order to maximize the resource sharing. however, it execute the optimal clock period selection algorithm.
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We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAs. Field programmable gate array(FPGAs) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAs are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.
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In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.
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In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.
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A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing cell array is proposed. It has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram. The constraints' length of trellis diagram is connected circularly so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.
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Recently, SystemC is one among the language observed. In Industry, there are many the languages that use Verilog. But, unskillful SystemC users must learn SystemC for conversion that from Verilog to SystemC and need time and effort for this. By these reason, feel necessity of easy and efficient conversion. This paper argues efficient methodology to change Verilog to SystemC. Abstract concepts of Verilog are proposed fittingly each one by one in SystemC.
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This paper proposes a new Sense Amplifier for MRAM. Current Sense Amplifier employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed Sense Amplifier simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speed as the latch-type Sense Amplifier in simulation and occupies only 85% of the area taken by the latch-type Sense Amplifier.
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This paper describes a design for a 2.5Gb/s serial data link CMOS transceiver based on the InfiniBand
$^{TM}$ specification. The transceiver chip integrates data serializer, line driver, Tx PLL, deserializer, clock recovery, and lock detector. The designed transceiver is fabricated in a 0.25${\mu}{\textrm}{m}$ CMOS mixed-signal, 1-poly, 5-metal process. The first version chip occupies a 3.0mm x 3.3mm area and consumes 450mW with 2.5V supply. In 2.5 Gbps, the output jitter of transmitter measured at the point over a 1.2m, 50Ω coaxial cable is 8.811ps(rms), 68ps(p-p). In the receiver, VCO jitter is 18.5ps(rms), 130ps(p-p), the recovered data are found equivalent to the transmitted data as expected. In the design for second version chip, the proposed clock and data recovery circuit using linear phase detector can reduce jitter in the VCO of PLL.L. -
본 논문에서는 노이즈를 고려한 PLL를 설계하였다. 30Mhz∼300Mhz으로 동작하는 VCO를 설계하였다. VCO를 평균 250Mhz으로 동작하도록 하고 reference 주파수, 62.5Mhz로 locking하는 PLL를 설계를 하였다. 300Mhz PLL의 기본적인 구조로 PLL은 PFD(Phase frequency detector), CP(Charge Pump), LF(Loop filter), VCO(Voltage controlled Oscillator)와 Divider로 구성되었다. PFD과 CP는 Dead Zone를 줄이고, 큰 gm를 가지도록 설계를 하였다. PLL에서 가장 중요한 블락인, VCO는 One Chip으로 설계하기 위해 Ring Oscillator로 설계를 하였다. 2.5V 62.5MHZ의 외부 신호를 300MHZ을 발진하는 VCO에서 분주하여 clock synthesizer를 설계하였다. 본 논문은 Hynix0.25공정을 사용하여 설계를 하였으며, 2.5V의 공급 전원을 사용하였다.
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This paper proposes a 2x oversampling method with a smart sampling for a clock and data recovery(CDR) circuit in a 2.5Gbps serial data link. In the conventional 2x oversampling method, the "bang-bang" operation of the phase detection produces a systematic jitter in CDR. The smart sampling in phase detection helps the CDR to remove the "bang-bang" operation and to improve the jitter performance. The CDR with the proposed 2x oversampling method is designed using Samsung 0.25
${\mu}{\textrm}{m}$ process parameters and verified by simulation. Simulation result shows the proposed 2x oversampling method removes the systematic jitter.e systematic jitter. -
This paper presents A/D converter for the signal processing of infrared sensor and CMOS image sensor. The A/D converter designed in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW at 2.5V supply voltage. This A/D converter is based on a pipeline architecture in which the number of bits converted per stage and the stage number are optimized to achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.
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This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35
${\mu}{\textrm}{m}$ CMOS process. -
본 논문에서는 분할된 스캔을 이용한 저전력 BIST 구조를 제안한다. 제안하는 BIST는 내부 스캔 패스를 회로의 구조적인 정보와 테스트 패턴 집합의 특성에 따라 4개의 스캔 패스로 분할하고 일부 스캔 패스에만 입력패턴이 인가되도록 설계하였다. 따라서 테스트 패턴 입력 시에 스캔 패스로의 쉬프트 동작 수를 줄임으로써 회로 내부의 전체 상태천이 수를 줄일 수 있다. 또한 4개로 분할되는 스캔패스의 길이를 고려하여 각 스캔 패스에 대해 1/4의 속도로 낮춰진 테스트 클럭을 인가함으로써 전체 회로의 전력 소모를 줄일 수 있도록 하였다. ISCAS89 벤치마크 회로에 대한 실험을 통하여 제안하는 BIST 구조가 기존 BIST 구조에 비해 최대 21%까지 전력소모를 줄일 수 있음을 확인하였다.
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In this paper, we propose a SDRAM Controller. The SDRAM is often used a mainstream memory as embedded system memory due to its short latency, burst access and pipeline features. The proposed Controller provides essential functions for SDRAM initialization, read/write accesses, memory refresh and Burst access. Furthermore, the proposed controller is implemented in the form of SOFT IP. Therefore, it reduces the designer's effort greatly.
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This paper proposes an 3D graphics rendering processor for portable device. One the most important factor is chip size for portable device, but the conventional 3D graphics rendering processor is not a suitable because the processor needs a lot of multiplication and division units. So the proposed architecture substitutes single precision floating point by 32 bit fixed point, and uses recursive units for the same operation such as color values(z, r, g, b, a) and texture values (s, t, u, v). In this approach, we reduce numbers of multiplications and divisions by 66.1% and 75% respectively at the sacrifice of performance degradation by 2.12%.
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A low-power design technique for lithium-ion Battery-Protection Integrated Circuit (BPIC) for multi cell configuration is proposed. The hardware sharing scheme with more precisely divided operating states in the detection range could reduce the power consumption significantly, especially during the normal state. The usefulness of the proposed scheme was confirmed through HSPICE simulations.
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A 64-point R2
$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94$mutextrm{s}$ . -
본 논문에서는 Coupling capacitance 변화량이 Static coupling capacitance 값보다 클 수 있다는 것을 새로운 테스트 회로를 이용하여 실험적으로 증명하였다. 테스트 회로는 배선의 지연시간이 배선의 저항보다는 배선의 정전용량에만 의존하도록 하여 배선의 지연시간을 평가함으로써 배선의 정전용량의 변화 즉, Coupling capacitance 의 변화량을 정확히 평가할 수 있도록 하였다. 0.15 ㎛ CMOS 기술을 이용하여 실험한 결과 In-phase crosstalk 인 경우에는 변화량이 Static coupling capacitance 보다 작았지만 Anti-phase 인 경우에는 Static coupling capacitance 보다 크게 나타남을 보여주고 있다. 따라서 배선에 의한 정확한 지연시간 평가를 위해서는 Crosstalk 이 발생한 경우의 Coupling capacitance 변화량을 정확히 반영하는 것이 매우 필요함을 알 수 있다.
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In this paper, The High-speed Low-power Analog-to-Digital Convener Archecture is proposed using the parallel S/H for High-speed operation. This technique can significantly reduce the sampling frequency per S/H channel. The Analog-to-Digital Converter is designed using 0.35
${\mu}{\textrm}{m}$ CMOS technology. The simulation result show that the proposed Analog-to-Digital Converter can be operated at 40Ms/s with 8-bit resolution and INL/DNL errors are +0.4LSB~-0.6LSB / +0.9LSB~-1.4LSB , respectively. -
This paper proposes a phase-locked loop (PLL) that achieves one-cycle lock acquisition by employing the lock-acquisition circuit (LAC). The LAC produces the initial analog voltage ( v
$_{c}$ ) that corresponds to the input frequency. When the transfer curve of the LAC matches that of the voltage-controlled oscillator (VCO), one-cycle locking can be possible. By HSPICE simulations, the proposed LAC is proved to be applicable to any kinds of PLL [1][2][3].].