Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
The Institute of Electronics and Information Engineers (IEIE)
- 기타
2002.06b
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Hot carrier induced device degradation is observed in thin-film, gate-all-around SOI transistor under DC stress conductions. We observed the more significant device degradation in GAA device than general single gate SOI device due to the degradation of edge transistor. Therefore, it is expected that the maximum available supply voltage of GAA transistor is lower than that o( bulk MOSFET or single gale SOI device.
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In this study, the electrical characteristics of 100v-Class LDMOSFET for high temperature applicat -ions such as electronic control systems of automo -biles and motor driver were investigated. Measurement data are taken over wide range of temperature(300k-SOOK) and various gate length(1.5 #m-3.0#m, step 0.3). In high temperature condition(>500k), drain current decreased over 30%, and specific on- resistance increased about three times in comparison with room temperature. Moreover, the ratio ROJBV, a figure of merit of the device, increased with increasing temperature.
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This study has been investigated that traps generated inside of the oxide and at the oxide interfaces by the stress bias voltage. The traps are charged near the cathode with negative charge and charged near the anode with positive charge. The charge state of the traps can easily be changed by application of low voltages after the stress high voltage. These trap generation involve either electron impact ionization processes or high field generation processes. It determined to the relative traps locations inside the oxides ranges from 113.4A to 814A with capacitor areas of 10
$^{-3}$ $\textrm{cm}^2$ The oxide charge state of traps generated by the stress high voltage contain either a positive or negative charge. -
A sensor array (35mm'! in diaphragm dimension) of 12 sensing elements with different operating temperatures was optimized with respect to thermal operation. This sensor array with single heater on a glass diaphragm over back-etched silicon bulk realizes a novel concept of a sensor array: an way of sensor elements operated at different temperatures can yield more information than single measurement. The proposed micro sensor array could provide well-integrated way structure because it has only single heater at the center of the diaphragm and used the various sensing properties of two kinds of metal oxide layers with various operating temperatures.
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We have been fabricated white organic light emitting diode with two-wavelength ard mixing blue emit in DPVBi (4, 4-bis(2, 2-diphenylvinyl)-1, 1 -biphenyl)layer and yellow emit in rubrene (5, 6, 11, 12-tetraphenylnaphthacene)as emitting layer which are controlled with thickness. This device emits white light emitting in CIE (0.29, 0.33), 1000cd/
$m^2$ at DC 18V. -
This paper describes a novel structure of NMOSFET with elevated SiGe source/drain region and ultra-shallow source/drain extension(SDE)region. A new ultra-shallow junction formation technology. Which is based on damage-free process for rcplacing of low energy ion implantation, is realized using ultra-high vacuum chemical vapor deposition(UHVCVD) and excimer laser annealing(ELA).
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MESFET was fabricated using 4H-SiC substrates and epitaxy The DC characteristics of 0.5 urn gate length, 400 urn gate width MESFET had
$I_{dss}$ =200 ㎃/mm, maximum transconductance of 12 ㎳/mm at Vrs=-4 V, V, Is=27 V. Thc device had an fT of 2.5 GHz and$f_{mdx}$ of 13.3 GHz at$V_{ds}$ =27 V and$V_{g}$ =-4 V. The fabrication and characterization of this device are discussed.d.d.d. -
We have been fabricated the white organic electroluminescent devices using vacuum evaporation method. The structure of the white OELD is Glass/1T0/NPB/DPVBi/AI
$q_{3:}$ Ru bren e/B CP/Alq$q_3$ /Al. We have got the white emission with two-wavelength that is mixing blue emission in DPVBi layer and orange emission in Al$q_{3:}$ Rubrene layer by varying tile doping concentrations of Rubrene and the thickness of NPB layer.yer. -
The Semiconductor Industrial are developed after 1940. It was called “Rice of Industrial”. It needs great effect in Electronics. It was developed highly in recent several years with semiconductor manufacturing equipments. Semiconductor manufacturing devices are developed “In-line” type in the first stage. But It was non-effective in modem many type process. Because this reason, Cluster type manufacturing equipments are proposed. Cluster have ability of many-type-process and effective-scheduling by circular type process chamber In this paper. we propose a real-time 3D monitoring and simulation of this semiconductor manufacturing equipments. By proposed monitoring method, we have capability real visual maintanance & virtual simulation. This effective visual 3D monitoring could apply another dangerous environment in entire industrial.
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This paper discusses the surface roughness of negative chemically amplified resists, SAL601 exposed by I-beam direct writing. system. Surface roughness, as measured by atomic force microscopy, have been simulated and compared to experimental results. Molecular-scale simulator predicts the roughness dependence on material properties and process conditions. A chemical amplification is made to occur in the resists during PEB process. Monte-Carlo and exposure simulations are used as the same program as before. However, molecular-scale PEB simulation has been remodeled using a two-dimensional molecular lattice representation of the polymer matrix. Changes in surface roughness are shown to correlate with the dose of exposure and tile baking time of PEB process. The result of simulation has a similar tendency with that of experiment.
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A new method is developed to extract model parameters of SiGe HBT equivalent circuit including the base impedance and base-collector junction capacitance. Using this method, all resistances and capacitances of SiGe HBT are independently determined from measured S-parameters using two-port parameter formula. This method is proposed to reduce possible errors generated from global optimization process, and its accuracy has been verified by finding good agreements between measured and modeled current / power gain up to 18 GHz.
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We have developed a Monte Carlo (MC) simulator for electron beam lithography in multi-layer resists and multi-layer substrates in order to fabricate and develop high-speed PHEMT devices for millimeter- wave applications. For the deposited energy calculation to multi-layer resists by electron beam in MC simulation, we modeled newly for multi-layer resists and heterogeneous multi-layer substrates. Using this model, we simulated T-gate or r-gate fabrication process in PHEMT device and showed our results with SEM observations.
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In this paper, transmission lines with low and high characteristic impedance (Z
$_{0}$ ) are fabricated and analyzed. The transmission lines are fabricated on the benzo-cyclo-butene (BCB) films of a low dielectric constant. For the low Z$_{0}$ , two types of coplanar waveguide (CPW) structures are fabricated, which include bottom-ground and double-ground type. Measurement shows that Z$_{0}$ values for each CPW type are 7.3 and 9.4$\Omega$ , respectively, at a signal line width of 100 #m. Whit the ratio between the spacing of bottom-ground and the signal line with becomes greater than 2.5, the Z$_{0}$ is nearly saturated. In addition, thin film microstrip lines fabricated using the BCB insertion layers show very low Z$_{0}$ of 25.5$\Omega$ , and this impedance is ~64 % of the values obtained from the BCB-based CPW structures of the same line width. Measurement result of CPW on BCB layer is 100.5 Ω.s 100.5 Ω. -
Moon, Tae-Jung;Hwang, Sung-Bum;Kim, Byoung-Kook;Ha, Young-Chul;Hur, Hyuk;Song, Chung-Kun;Hong, Chang-Hee 61
We have optimally designed and implemented by a monolithic microwave integrated circuit(MMIC) the low noise amplifier(LNA) of 5.8GHz band composed of receiver front-end(RFE) in a on-board equipment system for dedicated short range communication using a depletion-mode GaAs MESFET. The LNA is provided with two active devices, matching circuits, and two drain bias circuits. Operating at a single supply of 3V and a consumption current of 18㎃, The gain at center frequency 5.8GHz is 13.4dB, Noise figure(NF) is 1.94dB, Input 3rd order intercept point(lIPS) is 3dBm, and Input return loss(5$_{11}$ ) and Output return loss(S$_{22}$ ) is -l8dB and -13.3dB, respectively. The circuit size is 1.2$\times$ O.7$\textrm{mm}^2$ .EX>.>. -
The verification of software part and HW/SW interface suffer from the absence of the hardware platform at the end of partitioning and coding phase in design cycle. In this paper we present the design of easy verification for hardware design. Hardware and software engineer can verify their software program and hardware design for a chip that is emulated in proposed verification environment. Besides, designer can easily design the DEMO system.
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This paper proposed a new charge-shared switching MDAC for a pipelined A/D converter The proposed architecture accomplishes the same function of a conventional multiplying-digital-to-analog converter (MDAC). By adopting the proposed scheme, about 40% of the total capacitances could be reduced and the speed of the MDAC increases. The performance of the charge-shared switching MDAC has been Proved by HSPICE simulations.
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In this paper we present an integrated Hail sensor It for fan motors, fabricated in industrial bipolar process. As a discrete Hall sensor and signal processing circuitry In the fan motor system were Integrated into single chip a temperature dependence of Hall sensitivity and Hall offset voltage can be compensated and cancelled by on-chip circuitry. We Propose a novel temperature compensation of Hall sensitivity with negative temperature coefficient (TC) using the differential amplifier gain with Positive TC. After a package of the chip was sealed using a plastic Package 20 Pins, the thermal and magnetic characteristics were investigated. The obtained experimental results are in agreement with analytical predictions and have more excellent performance than\ulcorner conventional the fan motor system using discrete Hall sensor.
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In this paper, InP-based HBTs have been optimally designed by numerical simulation and fabricated by the self-aligned process. The structure of HBT was designed in terms of the current gain*f
$_{max}$ for the base and f$_{T}$ *f$_{max}$ for the collector. The designed structure produced the current gain of about 50 and the cutoff frequency and the maximum oscillation frequency of 87GHz and 2940Hz respectively. In addition, we present a study of the vertical and lateral etching of InP with the mask sides parallel to the principal crystallographic axes, [0101 and (001). This etching characteristics arc used to fabricate self-aligned HBT structures with reduced parasitic effects.s.s.s. -
We suggest binary image decryption system using two-wavc mixing in Photorefractive crystal. Compared with a conventional method, this method can make optical alignment easily, and brighten the encrypted image even if a small input signal, by index grating of photorefractive crystal. Also it can reconstruct the encrypted image by only reference beam in real time.
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A digital watermark is an invisible mark embedded in a digital image which used for copyright protection. In this paper, we propose a new optical watermarking system. A optical watermarking system is applied for digital watermarking by phase hologram and Mach-Zehnder interferometer. A optical watermarking technique to be hidden is phase modulated in a random patten, and its Fourier-transformed hologram image is superposed on a content image. The autentication information extract by using Mach-zehnder interferometer.
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It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.
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A procedural interface libary for IEEE Verilog 1364-2001 is developed. The lexer and scanner are developed to handle “Verilog-2001” which is the first major update to the Verilog language since its inception in 1984. Also the newly developed XML intermediate format for Verilog-2001 is Presented in the paper. By using the XML intermediate, it allows the portable and scalable development of various kinds of applications. The XML DTD(Document Type Definition) of Verilog is defined and the corresponding XML intermediate format is developed. The paper describes example application of code rule checker which is built using the language interface library.
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This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.
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Although asynchronous designs have become a promising way to develop complex modern digital systems, there is a few complete design framework for VLSI designers who wish to use automatic CAD tools. Especially, high-level synthesis is not widely concerned until now. In this paper we Proposed a method for high-level synthesis of asynchronous systems as a part of an asynchronous design framework. Our method performs scheduling, allocation, and binding, which are three subtasks of high-level synthesis, in simultaneous using a transformational approach. To deal with complexity of high-level synthesis we use neighborhood search algorithm such as Tabu search.
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This paper presents relationship between the dynamic behavior of an asynchronous linear pipeline (ALP) and the performance of the ALP as buffers are allocated. Then the relationship is used in order to characterize a local optimum situation on the buffer design space of the ALP. Using the characterization we propose an efficient algorithm optimizing buffer allocation on an ALP in order to achieve its average case performance. Without the loss of optimality, our algorithm works in linear time complexity so it achieves fast buffer-configuration optimization. This paper makes two contributions. First, it describes relationship between the performance characteristics of an ALP and a local optimum on the buffer design space of the ALP. Second, it devises a buffer allocation algorithm finding an optimum solution in linear time complexity.
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This paper describes a design of 8192-Point pipelined FFT/IFFT processor (PFFTSk) core for DVB-T and DMT-based VBSL modems. A novel two-step convergent block floating -point (75_CBFP) scaling method is proposed to improve the signal- to-quantization-noise ratio (SeNR) of FFT/IFFT results. Our approach reduces about 80% of memory when compared with conventional CBFP methods. The PFFTSk core, which is designed in VHDL and synthesized using 0.25-
${\mu}{\textrm}{m}$ CMOS library, has about 76,300 gates, 390k bits RAM, and Twiddle factor ROM of 39k bits. Simulation results show that it can safely operate up to 50-MHz clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-$mutextrm{s}$ . The SQNR of about 60-dB is achieved. -
In this paper, we construct cryptographic accelerators using hardware Implementations of HMACS based on a hash algorithm such as MD5.It is basically a secure version of his previous algorithm, MD4 which is a little faster than MD5 The algorithm takes as Input a message of arbitrary length and produces as output a 128-blt message digest The input is processed In 512-bit blocks In this paper, new architectures, Iterative and full loop, of MD5 have been implemented using Field Programmable Gate Arrays(FPGAS). For the full-loop design, the performance Is about 500Mbps @ 100MHz
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In this paper, we propose a bias random vector generator which can verify functions of microprocessor effectively. This generator is a pre-processor of assembly program, and defines pre-processor instructions which create random vector only in the part which the designer wants to verify. Therefore, this generator shows higher detection ration than any other generators. And, we can cut down design costs because of shortening a period for verifying function.
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This paper designed a cipher process, which used SEED-Algorithm that is totally domestic technique. This cipher processor is implemented by using SEED-cipher-Algorithm and pipeline scheduling architecture. The cipher is 16-round Feistel architecture but we show just 16-round Feistel architecture for brevity in this thesis. Of course, we can get the result of the 16-round processing by addition of control part simply. Furthermore, it has pipelined architecture, so the speed of cipher process is the faster than others when we performed a cipher a lot of data. The schedule-function can performed the two-cipher process simultaneously, such as using two-cipher processors.
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AE64000 is the 64-bit high-performance microprocessor that ADC Co. Ltd. is developing for an embedded environment. It has a 5-stage pipeline and uses Havard architecture with a separated instruction and data caches. It also provides SIMD-like DSP and FP operation by enabling the 8/16/32/64-bit MAC operation on 64-bit registers. AE64000 processor implements the EISC ISA and uses the instruction folding mechanism (Instruction Folding Unit) that effectively deals with LERI instruction in EISC ISA. But this unit makes branch prediction behavior difficult. In this paper, we designs a branch predictor optimized for AE64000 Pipeline and develops a AES4000 simulator that has cycle-level precision to validate the performance of the designed branch predictor. We makes TAC(Target address cache) and BPT(branch prediction table) seperated for effective branch prediction and uses the BPT(removed indexed) that has no address tags.
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This paper discusses the design of a sample-and -hold amplifier(SHA) that has a 12-bit resolution with a 100 MS/s speed. The sample-and-hold amplifier uses the open-loop architecture with hold-mode feedthrough cancellation for high accuracy and high sampling speed. The designed SHA is composed of input buffer, sampling switch, and output buffer with additional amplifier for offset cancellation Hard Ware. The input buffer is implemented with folded-cascode type operational transconductance Amplifier(OTA), and sampling switch is implemented with switched source follower(SSF). A spurious free dynamic range (SFDR) of this circuit is 72.6 dB al 100 MS/s. Input signal dynamic range is 1 Vpp differential. Power consumption is 65 ㎽.
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This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.
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Several charge Injection compensation circuits, such as, the dummy transistor circuit, the switched OP-amp circuit, the switched capacitor circuit, were fabricated and the test results were compared. The differences between SPICE simulation results and measurements were within around 10%.
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In this paper, a voltage controlled oscillator (VCO) with automatic amplitude control is designed using a 0.35
${\mu}{\textrm}{m}$ CMOS process. A cross-coupled PMOS pair is used for a negative resistance to compensate for the losses in the LC resonator, and an automatic\ulcorner amplitude control function is adapted to provide constant output power independent of the Q-factor of the LC resonator. The designed VCO operates in the 200MHz to 550MHz frequency range using different external resonators. The simulated phase noise is -128 dBc/Hz at 100KHz offset from the carrier frequency of 260MHz. It dissipates 0.㎽ from a 3V power supply. The area is 300${\mu}{\textrm}{m}$ x1201${\mu}{\textrm}{m}$ . -
The performance of a 1-bit DAC depends on that of the analog circuits. The mixed SC-CT (switched capacitor-continuous time) architecture is an effective design methodology for the analog circuits. This paper Proposes a new buffer scheme for the 1-bit digital-to-analog subconverter and a new SF-DSC(smoothing filter and differential-to-sig le converter) which performs both the smoothing filter and the differential-to-single convertor simultaneously.
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FFT/IFFT block is very important module to determine the performance of OFDM system. This block has been implemented using several FFT algorithms such as radix-2, radix-4 etc. However SRFFT algorithm has not been implemented because of the complexity for implementation. This paper proposes a serial-pipeline SRFfT for OFDM system. The serial-pipeline SRFFT is optimized to use a serial input and serial output. We have implemented the SRFFT block using anam 0.25 Um five-metal process. The simulation show that the SRFFT block can operate about 200MHz. This architecture could be adapted to IEEE 802.lla wireless LAN standard.
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This paper proposed a guideline for selecting the arithmetic circuit architecture. The guideline incorpo-rates the new concept of PDSP (power-delay-size product) and the weighting method. HSPICE simulations havc been performed to several full adders in order to prove the validity of the proposed guideline. We applied this guideline to select an optimized FA (full adder) architecture and successfully implemented the DAC's digital blocks.
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This paper presents an 1-D substrate resistance value expression and compares the measured wave-form data with the calculated 1-D resistance network model. The remaining part is devoted to the effectiveness of guard ring varying its width and number.
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As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.
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A protection integrated circuit which enables the stable operation of the rechargeable battery should be designed with a low-power architecture because it consumes the power of the battery. This paper proposed a low-power scheme especially when the several series-connected batteries are provided. By adopting a time sharing control of the batteries, the chip size and power consumption could be reduced.
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This paper is about a high-speed MAC (multiplier and accumulator) design applying radix-4 and radix-8 Booth's algorithm at the same time. The optimized hybrid radix design for high speed MAC has taken advantage of both a radix-4 and a radix-8 architectures. A radix-4 architecture meets high-speed, but it takes much more power and chip area than a radix-8 architecture. A radix-8 architecture needs less power and chip area than the other, but it has a bottleneck of generating three times the multiplicand problem. An optimized hybrid architecture performs the radix-4 multiplication partially in parallel with the generation of three times the multiplicand for use of the radix-8 multiplication. It reduces the concerned bit width of multiplier in radix-8 multiplication.
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본 논문에서는 600Hz 무선 LAN 시스템에 탑재를 위한 600㎓ 대역 전력증폭기 모듈을 개발 하였다. 600㎓ 대역 전력증폭기 모듈에 실장된 600㎓ 대역 전력증폭기 MMIC는 ETRI에서 설계 및 제작한 것으로 칩의 크기는 2.80 × 1.75㎟이며, on-wafer측정을 하여 얻은 결과는 동작 주파수 58~620Hz에서 소신호 이득은 12.4dB이고, 최대 소신호 이득은 59~60G보z에서 ISdB이며, 출력전력(Pldn)은 16.3~16.7dBm을 얻었다. 이와 같은 특성을 갖는 전력증폭기 MMIC를 사용하여 모듈을 제작하였으며, RF feed line을 위해 Rogers 사의 R03003 기판을 사용하였다. 모듈의 입출력은 동작 주파수 대역에 적합한 WRl5라는 waveguide 형태를 사용하였고, DC 바이어스 공급을 위해 3.5㎜ K-connector를 사용하였다 제작한 모듈의 크기는 40 × 30 × 15㎣이며, 최적의 성능을 얻고자 tuning bar를 상하로 이동하여 최적점을 찾았으며 나사로 고정하여 상태를 유지하도록 하였다. DC 바이어스 및 RF feed line과 칩의 연결은 본딩에 의한 인덕턴스를 최소화하기 위하여 3mil 두께의 리본 본딩을 하였다 전력증폭기 모듈을 측정한 결과, 동작주파수 600㎓ 대에서 소신호 이득은 6dB 이상, 입력 정합은 -lOdB 이하, 출력 정합은 -4dB 이하로 측정되었긴, 출력전력은 SdBm 이상으로 측정되었다. 동국대에서 제작한 600Hz 무선 LAN 시스템에 전력증폭기 모듈을 시스템 송신부에 탑재 시험한 결과, 동영상을 실시간으로 전송하는데 성공하였다.
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In this paper, Amorphous silicon on glass substrate was recrytallized to poly-crystalline silicon by solid phase crystallization(SPC) technology The active region of thin film transistor(TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain(LDD) structure was measured and analyzed. As a results, analyzed TFT's reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations
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In this work, a Voltage-to-Frequency Converter.(VFC) in which the output frequency is proportional to the input voltage is proposed. To obtain temperature stable characteristics the VFC is designed by using two bandgap references. The difference between simulated and calculated values is less than about 5% in output characteristics. In the VFC using BiCMOS the temperature variation of sample output frequencies is less than
$\pm$ 0.5% in the temperature range -$25^{\circ}C$ to 75$^{\circ}C$ . And the CMOS VFC has error less than$\pm$ 0.8% in the temperature range -$25^{\circ}C$ to 75'$^{\circ}C$ . -
This paper presents the improvement of the boron penetration and the reverse short channel effect (RSCE) in the 130nm W/WNx/Poly-Si dual gate PMOSFET for a high performance embedded DRAM. In order to suppress the boron penetration, we studied a range in the process heat budget. It has shown that the process heat budget reduction results in suppression of the boron penetration. To suppress the RSCE, we experimented with the halo (large tilt implantation of the same type of impurities as those in the device well) implant condition near the source/drain. It has shown that the low angle of the halo implant results in the suppression of the RSCE. The experiment was supported from two-dimensional(2-D) simulation, TSUPREM4 and MEDICI.
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In this paper, presents a 1.8V 8-bit 300MSPS CMOS Subranging Analog to Digital Converter (ADC) with a novel reference multiplex is described. The proposed hか converter is composed of Sub A/D Converter block, MUX (Multiplexer) block and digital block. In order to obtain a high-speed operation, further, a novel dynamic latch, an encoder of novel algorithm and a MUX block are proposed. As a result, this A/D Converter is operated 100MHz input frequence by 300MHz sampling rate.
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A large area inductively coupled plasma which is applicable to LCD processing is built with a modified single loop RF antenna. Combination of parallel and series paths of RF current through the antenna induces local enhancement of plasma density, which in turn provides uniform plasma density near the substrate. The plasma density distribution is measured and compared with that of the conventional single loop antenna. Aisotropic etching of photoresist is performed, and it is found that etch uniformity is improved by 3% from 15% of the conventional etcher over 350
$\times$ 300mm glass substrates. Photoresist etching rate and uniformity can be further improved by applying a periodic weak axial magnetic fieid. -
An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.
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As the mask design rules get smaller, the probability of the process failure becomes higher doc to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method Is applied with the rule based optical\ulcorner proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design rule is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.
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A double-heterostructure AIGaAs/GaAs PHEMT (Pseudomorphic High Electron Mobility Transistor) using digital recess has been successfully realized. Futhermore, the differences of gm,nax, fT, fmax between two samples are as low as 0.62%, 1.58% and 2.56 % respectively. Experimental results are presented demonstrating the etch rate and Process invariability with respect to hydrogen peroxide and acid exposure times with uniformity among devices on a sample.
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In this paper, we have investigated electronical chara-cteristics of power LDMOSFETS having different ex-tended gate lengths(1.B
${\mu}{\textrm}{m}$ , 2.4${\mu}{\textrm}{m}$ , 3.O${\mu}{\textrm}{m}$ ) in the temperature range of 300k-500K. The results of this study indicate that on-resistance, breakdown voltage increase with temperature. and drain current, threshold voltage, transconductance decrease with temperature. Particular the facts, we observed that Le is the more increase, on-resistance is the more decrease. because every conditions are fixed normal states, only change the Le. As a result, Ron/BV, known for a figure of merit of power device, increase with temperature. -
Recently, simulation of Chemical Mechanical Polis hing is becoming more important because Process parameters on the material removal rate are complicated. And pattern-depent effects are a key concern in CMP processes. In this paper, we have been studied the changes of pattern density vs. oxide thickness with Stine's simulation model. We also have estimated the effective density using optimal window size with density mask, and have made a study of the change of oxide thickness as a function of polishing time.
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The adhesion effect between the oxide layer and the metal layer has been studied by RTP anneal. Two types of oxides, BPSG and P-TEOS, were used as a bottom layer under multi-layered metal film. We observe the interface between oxide and metal layer using SEM (scanning electron microscopy), TEM (transmission electron microscopy), AES (auger electron spectroscopy). Adhesion failure was occurred by interfacial reaction between the BPSG oxide and the multi-layered metal film at 650"C RTP anneal. The phosphorus rich layer was observed at interface between BPSG oxide and metal layer by AES and TEM measurements. On the other hand adhesion was a)ways good in the sample used P-TEOS oxide as a bottom layer. We have known that adhesion between BPSG and multi-layered metal film was improved when the sample was annealed below
$650^{\circ}C$ .TEX>. -
In this paper, etching characteristics of Zr-silicate in Ar/ClrCH4 plasma is studied, and possible plasma damage is investigated by fabricating MIS capacitors. We'could increase the selectivity to near 2 while keeping the etch rate of Zr-silicate to about 70 nm/min. Leakage current and flat band voltage shift of PUZr-silicate/si capacitors are measured before and after plasma etching. Using capacitor patterns with the same area but different circumference lengths, we try to separate etching damage mechanisms and to optimize the process. The leakage current of 1.2
$\times$ 10-3 A/cm2 and smaller capacitance variation of 0.2 nF at -2V are obtained in Ar/Cl2/CF4 plasma at 200 W RF power -
This paper has been designed and fabricated C-type micro, high-performance solenoid RF chip inductors with the size of 1.58
$\times$ 0.82r0.94m0. The high frequency characteristics of simulated results obtained by HFSS were compared to those of measured results obtained by RF Impedance/Material Analyzer (HP16193A). Although the simulated inductance values were two times larger than the measured values and there are discrepancies in SRFs between simulated and measured values, it was observed that tile Q-factor values for fabricated inductors could be predicted from the simulated values. -
In this W, a NiSi technology suitable for sub-100nm CMOS sevice is proposed. It seems that capping layer has little effect on the sheet resistance and junction leakage current when there is no thermal treatment. However, there happened agglomeration and drastic increase of Junction leakage current without capping layer. In other word, capping layer especially TiN capping layer is highly effective in suppressing thermal effect. It is shown that the sheet resistance of 0.12
${\mu}{\textrm}{m}$ linewidth and shallow p+/n junction with NiSi were stable up to 700 t /30 minute thermal treatment. -
The dependence of NiSi properties such as sheet resistance and cross-sectional profile on the dopants was characterized. There was little difference of sheet resistance between various dopants such as As, p, BF2 and B just after R'n formation of NiSi. However, the NiSi properties showed strong dependence on the dopants when thermal treatment was applied after RTf formation. BFa .implanted silicon was the best stable property while As implanted one was the worst. The main reason of the excellence property of BF2 sample is believed to be the retardation of Ni diffusion by the F. Therefore, retardation of Ni diffusion is very desirable fur high performance NiSi technology.
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In this paper, the influence of Si surface damage on the NiSi formation has been characterized. The silicon surface is damaged using ion beam type spotter. Then, the effect of H2 anneal and TiN capping layer on the damaged has also been analyzed. The sheet resistance of NiSi formed on damaged Si increased rapidly as the damaging time increases while thermal stability of damaged NiSi was stabler than the undamaged one. In the case when H\ulcorner anneal and TiN capping layer were applied together, the characteristics of NiSi shows a little improvement of the sheet resistance.
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we have studied the characteristics of PHEMT's with gate recess etching method. The DC characterization of PHTMT fabricated with the wide single recess methods is a maximum drain current density of 319.4 ㎃/mm and a peak transconductance of 336.7 ㎳/mm. The RF measurements were obtained in the frequency range of 1~50GHz. At 50GHz, 3.69dB of 521 gain were obtained and a current gain cut-off frequency(f
$_{T}$ ) of 113 CH and a maximum frequency of oscillation(f$_{max}$ ) of 172 Ghz were achieved from this device. On the other hand, a maximum drain current of 367 mA/mm, a peak transconduclancc of 504.6 mS/mm, S$_{21}$ gain of 2.94 dB, a current gain cut-off frequency(f$_{T}$ ) of 101 CH and a maximum frequency of oscillation(f$_{max}$ ) of 113 fa were achieved from the PHEMT's fabricated by the .narrow single recess methods.methods. -
In Currently, OTFTS are actively studied around the world because they are expected to create new novel applications, which can not be implemented by the conventional Si semiconductor, due to the unique characteristics of organic materials. In this paper, the hole field effect mobility has been improved to the level of a-Si TFTs with 0.3cm2/V.sec, simply applying the surface treatment process on the gate with organic molecules. In addition, the model has been suggested and the temperature dependence of hole mobility analyzed.
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This paper describes the pixel of AMOLED(act ive matrix organic light emitting diode) driving circuit by poly-sl technology. The area per pixel is 278um
$\times$ 278um in 120$\times$ 160(2.2 inch) Driving the OLEDS with active matrix leads to the lower voltage operation, the lower peak pixel currents and the display with much greater efficiency and brightness The role of the active matrix is to provide a constant current throughout the entire frame time and is eliminating the high currents encountered In the passive matrix approach, This design can support the high resolutions expected by the consumer because the current variation specification is norestricted. The pixel has been designed driving TFT threshold voltage cancellation circuit and wide aperture ratio circuit that communizes 4 pixel. The test simulation results and layout are 11% per threshold-current var Eat ion and 12.5% the aperture ratio of increase. -
LCD is not very expensive and according to the principle that twisted-nematic LCD can modulate by electric signal, lots of researches been developed about many of theory, methods of design and calculating parameters effectively. In 1999 J. A. Davis et ai. proposed the method of deciding upon extraordinary and ordinary axis direction, which is based on Blazing Effect, inspect into changes of diffraction patterns. But in laboratory, it is difficulty to observe 5th or 6th diffraction pattern, and not clear in mathematical. In this paper, illuminating circular polarized beam been to TN LCD (twisted-nematic LCD), we found extraordinary axis direction with inspecting into maximum intensity distribution appeared in the side of analyzer Using Jones matrix method, we endowed with mathematical propriety.
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In this paper, we propose a bias random vector generator which can verify functions of microprocessor effectively. This generator is a pre-processor of assembly program, and defines pre-processor instructions which create random vector only in the pall which the designer wants to verify. Therefore, this generator shows higher detection ration than any other generators. And, we can cut down design costs because of shortening a Period for verifying function.
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This paper analyze the characteristics of three multipliers in finite fields GF(2m) from the point of view of processing time and area complexity. First, we analyze structure of three multipliers; 1) LSB-first systolic array, 2) LFSR structure, and 3) CA structure. To make performance analysis, each multiplier was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that LFSR structure is best from the point of view of area complexity, and LSB systolic array is best from the point of view of processing time per clock.
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Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.
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In this paper, a new structure of 1024-bit high-speed RSA cryptosystem has been proposed and implemented in hardware to increase the operation speed and enhance the variable-length operation in the plain text. The proposed algorithm applied a radix-4 Booth algorithm and CSA(Carry Save Adder) to the Montgomery algorithm for modular multiplication As the results from implementation, the clock period was approached to one delay of a full adder and the operation speed was 150MHz. The total amount of hardware was about 195k gates. The cryptosystem operates as the effective length of the inputted modulus number, which makes variable length encryption rather than the fixed-length one. Therefore, a high-speed variable-length RSA cryptosystem could be implemented.
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In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed He multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.
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This paper proposes new driving methods for designing a driver independent of the current property of organic light emitting diodes (OLED) displays. The proposed methods are the Look-Up Table (LUT) and the Pulse Width Modulation (PWM). The LUT is used to handle the amount of the current for driving the OLED display panel and the PWM is applied to represent the gray scale on the OLED display panel. Segment and common drivers were implemented using delay circuits to prevent short-circuit current and a DC-DC converter was designed to supply the drivers with a power source. In particular, tile proposed methods are used for the manufacturing of 1.8" 128
$\times$ 128 dot passive matrix OLED display panel. The designed circuit was fabricated using 0.6w, 2-poly, 3-metal, CMOS process and applied to the Personal Communication System (PCS) phone successfully.ully. -
Application of electronic nose and PLD chip design was developed to be used in gas discrimination system for limited kinds of gas. An array of 4 metal oxide gas sensors with different selectivity patterns were used in order to measure gases. BP(Back Propagation) algorithm was designed and implemented on CPLD of two hundred thousand gate level chips by VHDL language for processing input signals from 4 kinds of gas sensors. This module successfully discriminated 4 kinds of gases and displayed the results on LCD and LED. The developed module could be used for various applications in the field of food process control and alcohol judgment.
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This paper describes the design and implementation results of JPEG core, based on the ITU-T Recommendation T.81. We designed the RTL circuit in Verilog HDL, making reference to the JPEG program from the Independent JPEG Group. The circuit has been simulated with Verilog-XL, synthesized with Design Compiler and verified using Altera FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in image processing SOC.
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An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18
${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply. -
In this paper, we discuss the design of high gain low noise amplifier by using the 0.2sum CMOS technology. A cascode inverter is adopted to implement the low noise amplifier. The proposed cascode inverter LNA is one stage amplifier with a voltage reference and without choke inductors. The designed 2.4GHz LNA achieves a power gain of 25dB, a noise figure of 2.2dB, and power consumption of 255㎽ at 2.5V power supply.
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(Korea Information Security Agency) is designed by using VHDL to Implement hardware architecture It has been adopted by most of the security systems in Korea SEED Is designed to utilize the S-boxes and permutations that balance with the current computing technology It has the Feistel structure with 16 rounds The same procedure for data encryption and decryption makes possible an easy and practical hardware implementation. The primary functions used In SEED are F function and G function. This paper proposes an Iterative architecture of F function, a modified architecture of G function and an Iterative architecture of key scheduling algorithm. The designed SEED encrypts and decrypts exactly the test vectors It is expected to extend to various application fields If the design of control blocks Is added.
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Recently, AMBA(Advanced Microcontroller Bus Architecture) is used as common system bus at embedded system. In this paper, we described test method of peripheral device which is connected to AMBA according to the bus interface defined by AMBA protocol We implemented one of the APB(Advanced Peripheral Bus) peipheral module, GPIO(General Purpose Input/output), and tested its functionality as il is connected to the AMBA system.
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Nowadays variable delay arithmetic units have been used for implementing a datapath of\ulcorner target system in pursuit of performance improvement. However. adoption of variable delay arithmetic units requires modification of a typical synchronous control units design methodology. There is a representative approach, which is called a monolithic approach. Although its results are good, its proposed methodology may cause critical problems in the aspects of area and performance with the size increase of initial system specifications. In order to solve this problems, a distributed approach is suggested. Experimental results show that the Proposed method can guarantee original performance of an initial system specification with minimized additional area increase.
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In this paper, we present a SystemC model of a 32-Bit RISC core wi)ich is based on the ARMTTDMI architecture. The RISC core model was first modeled in C for architecture verification and then refined down to a level that allows concurrent behavior lot hardware timing using the SystcmC class library. It was driven in timed functional level that uses handshake protocol. It was compiled using standard C++ compiler. The functional simulation result was verified by comparing the contents of memory, the result of execution with the result from the ARMulator of ADS(Arm Developer Suite).
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The traditional debug tools for chip tests and software developments need a huge investment and a plenty of time. These problems can be overcome by Embedded Debugger based the JTAG boundary Scan Architecture. Thus, the IEEE 1149.1 standard is adopted by ASIC designers for the testability problems. We designed the RED(Reusable Embedded Debugger) using the JTAG boundary Scan Architecture. The proposed debugger is applicable for not a chip test but also a software debugging. Our debugger has an additional hardware module (EICEM : Embedded ICE Module) for more critical real-time debugging.
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This paper purpose design and implementation of system bus for the effective interconnection between peripheral device and 32-bit microprocessor. The designed system bus support general bus protocol. Also, it is optimized for 32-bit microprocessor. It is divided into two system. high performance system bus and Peripheral system bus.
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In data transmission at the digital satellite broadcasting systems, the delay and spread are caused whit receiving original signals from the transmitter in the receiver. So, there are some problems in data fast transmission. Also, transmitted signals ate received in stale of the combination of transmission delay and noise of channel. The affect of channel noise is reduced when increasing transmission power, but as signal interference due to the transmission delay and spread of channel increase in proportion to the transmission power, there is a problem in spite of increasing the transmission power. And there is the problem to add ISI(inter symbol interference) because the property of the channel is limo-varying due to relative moving in the transceiver Therefore, in this paper, a pulse shaping filter for the high-speed service in digital satellite broadcasting systems was designed and reduced the ISI.
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The importance of protection for information is increasing by the rapid development of information communication and network. Asymmetric crypto-system is the mainstream in encryption system rather than symmetric cryptosystem by above reasons. But asymmetric cryptosystem is restricted in applying to application fields by the reason it takes more times to process than symmetric cryptosystem. In this paper, the proposed cryptosystem uses an algorithm that combines block cipherment with stream ciphcrment. Proposed cryptosystem has a high stability in aspect of secret rate by means of transition of key sequence according to the information of plaintext while asymmetric /symmetric cryptosystern conducts encipherment/decipherment using a fixed key Consequently, it is very difficult to crack although unauthenticator acquires the key information. So, the proposed encryption system which has a certification function of asymmetric cryptosystcm and a processing time equivalent to symmetric cryptosystcm will be highly useful to authorize data or exchange important information.
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This paper presents new fast scalar multiplier of elliptic curve cryptosystem that is regarded as next generation public-key crypto processor. For fast operation of scalar multiplication a finite field multiplier is designed with LFSR type of bit serial structure and a finite field inversion operator uses extended binary euclidean algorithm for reducing one multiplying operation on point operation. Also the use of the window non-adjacent form (WNAF) method can reduce addition operation of each other different points.
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In this Paper, we introduced 32 bit SOC implementation for multi-application Smart Card and described the methodology for reducing power consumption. It consists of ARMTTDMI micro-processor, 192 KBytes EEPROM, 16 KB SRAM, crypto processors and card reader interface based on AMBA bus system. We used Synopsys Power Compiler to estimate and optimize power consumption. Experimental results show that we can reduce Power consumption up to 62 % without increasing the chip area.
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Due to the increased complexity and size of digital system and the need of the H/W-S/W co-design, C/C++ based system design methodology gains more Interests than ever in EDA field. This paper suggests the methodology in which handshake module corresponding to each basic statement of C is provided of the form of STG(Signal Transition Graph) and then, C statements is synthesized into asynchronous circuit through syntax-oriented translation. The 4-phase handshaking protocol is used for the communications between modules, and the modules are synthesized by the Petrify which is asynchronous logic synthesis CAD tool.
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This paper is proposed about an efficient pipelined architecture for 3D graphics accelerator to reduce Cache miss ratio. Because cache miss takes a considerable time, about 20∼30 cycle, we reduce cache miss ratio to use pre-fetch. As a result of simulation, we figure out that the miss ratio of cache depends on the size of tile, cache memory and auxiliary cache memory. We can save 6.6% cache miss ratio maximumly.
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In this paper, we consider the problem of CLB based CPLD technology mapping for power minimization in combinational circuit. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" and "feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results show that our approach is shown a decrease of 30.5% compared with DDMAP and that of 15.63% for TEMPLA in the Power consumption.
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WSW(Wrap Side Wall) is proposed to decrease junction electric field in this paper. WSW process is fabricated after first gate etch, followed NMI ion implantation and deposition & etch nitride layer New WSW structure has buffer layer to decrease electric field. Also we compared the hot carrier characteristics of WSW and conventional. Also, we design a test pattern including pulse generator, level shifter and frequency divider, so that we can evaluate AC hot carrier degradation on-chip.
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This paper presents a family of continuous conduction mode with constant-switching pulse width modulator controllers. Unified implementation of quasi steady state approach for various DC-DC converters topoiogies is illustrated. The property and control low for quasi-state approach will be discussed in this paper. The different procedures will be discussed in details with different results for five commonly used DC-DC converters. Both trailing and leading edge pulse width modulation are used. Leading edge modulation can some times lead to simpler control circuitry as will be demonstrated in some circuits. These controllers do not require the multiplier in the voltage feed back loop, error amplifier in the current loop and rectified line voltage sensor, which are needed by traditional control methods. Controller examples and design arc analyzed.