Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
The Institute of Electronics and Information Engineers (IEIE)
- 기타
2000.11b
-
This paper shows the high performance as a photodetector of InGaP/GaAs HPT with 3-terminal caused by its inherent good electrical properties compared with AIGaAs/GaAs HPT. InGaP/GaAs HPT produced the high optical gain of about 61 where HPT is biased at Vc=3V, Iв=2
${\mu}\textrm{A}$ with an input optical power of 1.23㎼. This is 2.5 times higher than that of AIGaAs/GaAs HPT. And we examined that the optical gain of HPTs becomes larger when operating in 3-terminal configuration rather than 2-terminal with the floating base. for a given base current of 2${\mu}\textrm{A}$ , the optical gain is enhanced about 18% in the InGaP/GaAs HPT and about 27% in the AIGaAs/GaAs HPT over that of the 2-terminal device. -
InP/lnGaAs heterojunciton phototransistors (HPTs) with transparent emitter contacts were fabricated and characterized. Indium Tin Oxide was RF sputtered for the emitter contacts. By comparison with InP/InGaAs HBTs, the dc characteristics of InP/lnGaAs HPTs demonstrated offset voltage due to ITO emitter contacts and similar common emitter current gain. The model parameters were extracted and a simple SPICE simulations were performed.
-
A quantum-wire field effect transistor(QW-FET) using asymmetric double InGaAs channel and Si-delta doped barrier has been fabricated. It exhibited good modulation and saturation characteristic in the range of
${\mu}\textrm{A}$ current level. For estimated channel width of 150nm QW-FET, maximum transconductance was about 400 mS/mm which is higher than a conventional heterostructure FET(HFET) with the same epi-structure. -
We have enhanced the yield of 0.25
${\mu}{\textrm}{m}$ T-gate$Al_{0.25}$ G$a_{0.75}$ As/I$n_{0.2}$ G$a_{0.8}$ As P-HEMT using three-layer E-beam lithography process and selective etching process. The three-layer resist structure (PMMA/copolymer/ PMMA=2000$\AA$ /3000$\AA$ /2000$\AA$ ) and three developers (Benzene:IPA=1:1,Methanol:IPA =1:1,MIBK:IPA=1:3) were used for fabrication of a wide-head T-gate by the conventional double E-beam exposure technology. Also 1 wt% citric acid:$H_2O$ $_2$ :N$H_{4}$ OH(200m1:4ml:2.2ml) solution were used for uniform gate recess. The etching selectivity of GaAs over$Al_{0.25}$ G$a_{0.75}$ As is measured to be 80. So these P-HEMT processes can be used in X-band MMIC LNA fabrication.ion.ion.ion. -
This paper introduces the design and implementation of a Ku-band 5-bit monolithic phase shifter with a ceramic package. The 5-bit phase shifter MMIC was designed and fabricated by using GaAs MESFET switches. The packaged phase shifter demonstrates a phase error less than 11.3
$^{\circ}$ RMS and an insertion loss variation less than 1.0㏈ RMS for 13∼15㎓. For all 32 states, an insertion loss is measured to be 12.2${\pm}$ 2.2㏈, an input return loss more than 5.0㏈, and an output return loss more than 6.2㏈ from 13㎓ to 15㎓. The chip size of the 5-bit phase shifter MMIC is 2.35${\times}$ 1.65mm$\^$ 2/ including digital control circuits. The size of the ceramic packaged phase shifter is 7.2${\times}$ 6.2mm$\^$ 2/. -
In this paper, three types of organic electroluminescent devices(OELD) were fabricated on mechanically flexible plastic substrate by using vacuum deposition method. The devices consist of a hole transporting material such as TPD, a light-emitting material such as Alq
$\sub$ 3/ and an electron transporting material, blocking material such as PBD. Electrical and optical properties of these OELDs were measured. This paper shows that organic small molecules based on OELD can be successfully deposited on a flexible plastic substrate. This points open the potential for low cost mass production of flexib]e displays, including roll to roll processing. -
Meta1-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/LiNbO
$_{3}$ /AIN/Si structure were successfully fabricated. AIN thin films were made into metal-insulator-semiconductor(MIS) devices by evaporating aluminum in a dot array on the film surface. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V ) characteristic is 8. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$ 10$^{-8A}$ $\textrm{cm}^2$ order at the electric field of 500㎸/cm. A typica] value of the dielectric constant of MFIS device was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500㎸/cm was about 5.6$\times$ 10$^{13}$ $\Omega$ .cmcm -
Active-controlled field emitter arrays (ACFEAs) are developed by monolithically integrating molybdenum field emitter arrays with amorphous silicon thin film transistors (a-Si:H TFTs) on glass substrate. Transfer and output characteristics of the fabricated ACFEAs showed that the emission currents of FEAs can be accurately controlled by the gate bias voltages of TFTs. Also, the emission currents of the ACFEAs kept stable without any fluctuations during the 30 min-operation.
-
This paper has been studied on characteristics of organic light-emitting device with various cathode materials. These catode materials were Al:Li(5%), Al, Cu, CsF/Al. And in these devices, HTL(hole transfer layer) was TPD and EML(emitting layer) was Alq
$\sub$ 3/. We studied the I-V characteristics for each device. And then, the turn-on voltage of device for Al-Li(5%), Al, Cu, CsF/Al cathode were 7, 9, 13, 3V respectively. So, the CsF/Al cathode is superior to other cathode materials for I-V characteristics. -
Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi
$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. -
DC Gummel-Poon SPICE model parameter extraction program has been implemented. This program extracts the parameters from measured data using Levenberg-Marquardt algorithm. Measured data consist of forward and reverse Gummel plot, forward and reverse output characteristics and RE and RC measurements.
-
This paper presents an efficient method for estimating maximum simultaneous switching noise(SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use a-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions. Our method predicts the maximum SSN values more accurately as compared to existing approaches even in more practical cases such that there exist some of output drivers not in transition.
-
This paper describes a single transistor type ferroelectric field effect transistor (1T FeFET) memory celt scheme which can select one unit memory cell and program/read it. To solve the selection problem of 1T FeEET memory cell array, the row direction common well is electrically isolated from different adjacent row direction column. So, we can control voltage of common well line. By applying bias voltage to Gate and Well, respectively, we can implant IT FeEET memory cell scheme which no interface problem and can bit operation. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.
-
As the density of memories increases, unwanted interference between cells and coupling noise between bit-lines are increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. From now on, conventional test algorithms have focused on faults between neighborhood cells, not neighborhood bit-lines. In this paper, a new algorithm for NPSFs, and neighborhood bit-line sensitive faults (NBLSFs) based on the NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a three-cell layout which is minimum size for NBLSFs detection is used. To consider faults by maximum coupling noise by neighborhood bit-lines, we added refresh operation after write operation in the test procedure(i.e., write \longrightarrow refresh \longrightarrow read). Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, conventional pattern sensitive faults, and neighborhood bit-line sensitive faults.
-
In this paper, we propose two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistor 1 and 2 employ a P-type folded composite transistor and an electronic zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried oui using 0.25
$\mu\textrm{m}$ n-well process with 2.5V supply voltage. -
DSP is used for processing the digital data in such as the multimedia applications. Because the digital data of high rate is demanded more and more, high performance is increasingly required in DSP. In this paper, we discuss important issues for development of high performance DSP, analyze architectures of several commercial DSP chips, and propose a new architecture. Finally, we show that the new architecture has the highest performance.
-
The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+PlusII and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.
-
This paper presents a new algorithm for allocating the data path to achieve the minimum power consumption under the constraints of minimum hardware resources. In order to minimize the power consumption, the proposed algorithm tries to minimize the input transitions of functional units, unnecessary computations, and size of interconnects in a greedy manner during a]location. Experimental results using benchmarks indicate the proposed algorithm achieves 17.5% power reduction on average, when compared with the genesis-lp[1]high-level synthesis system.
-
This paper describes a delay locked loop with selective starting point for use in a high-frequency systems. SSRDLL (selective starting point RDLL) has been simulated in a 0.25
$\mu\textrm{m}$ standard n-well CMOS process parameter to realize a fast lock-on time. This DLL is shown to be insensitive to variations in PVTL. The simulated lock time of the proposed SSRDLL is within 4 clock cycles at 333㎒ clock input. -
This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25
$\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results. -
This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.
-
This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65
$\mu\textrm{m}$ , 3.3V supply. -
New locking algorithm of DLL is proposed to improve the locking speed and low power dissipation in this paper, In spite of using the architecture of delay controller, low power consumption is acquired by operating only one controller at once and fast locking speed is accomplished by initial setting from the coarse controller. The proposed DLL circuit is operated from 50MHz to 200MHz and locked within 6 cycle at all of operating frequency.
-
Kim, Myung-Jin;Lee, Hoon;Choi, In-Gyu;Kim, Jong-Eun;Yang, Tae-Ouk;Choi, Sung-Hyuk;Park, Jong-Sik 100
In this paper, we designed the equalizer optimized for VDSL modem chip using QAM method. The equalizer is capable of variable constellation. The equalizer was coded using VHDL and the logic simulation was performed. The test vector were generated based on the channel environments using MATLAB. -
We designed and implemented the RFIC(RF front-end IC) for DTV(Digital TV) tuner. The DTV tuner RF front-end consists of low noise IF amplifier fur the amplification of 900 MHz RF signal and down conversion mixer for the RF signal to 44MHz IF conversion. The RFIC is implemented on ETRI 0.8u high resistive (2㎘ -cm) and evaluated by on wafer, packaged chip test. The gain and IIP3 of IF amplifier are 15㏈ and -6.6㏈m respectively. For the down conversion mixer gain and IIP3 are 13㏈ and -6.5㏈m. Operating voltage of the IF amplifier and the down mixer is 5V, current consumption are 13㎃ and 26㎃ respectively.
-
The electrical characteristics of MQFP packages have been measured in RF regime. The s-parameter of the lead frame has been measured using the test fixture on which the do-capped package was mounted. A simple lumped equivalent circuit modeling of the lead frame and the test fixture can provide reasonable model parameters up to the frequency of 200 MHz.
-
This paper describes the algorithm, architecture and design of the circuit implementing motion tracing features based on the edge detection. The Sobel operation was used to compute the edges of moving objects. Motion tracing is performed by searching for the center of the edges for each frame and adding those centers. The edger and the centers of the moving object from camera were displayed in the monitor and verified using Xillinx FPGA.
-
The Process of Inner Product has been widely used in a DSP. But it is difficult to implement by a dedicated hardware because it needs many computation steps for multiplication and addition. To reduce these steps, it is essential to design efficient hardware architecture. This paper proposes the design method of adder-based distributed arithmetic for implementation of DCT module and the automatic design of summation-network which is a core block in the proposed design method. Finally, it shows that the proposed design method is more efficient than a ROM-based distributed arithmetic which is the typical design method.
-
In this paper, A target architecture and interface synthesizer are proposed for processor-embedded codesign. The target architecture has the form of ARM processor based on AMBA. The interface synthesizer automatically generates an interface circuit for the communication between HW and SW. A memory map is used as the communication channel and an interrupt-based interface is applied for synchronized communication between HW and SW modules. In order to verify the function and performance of proposed target architecture and the interface synthesizer, practical test example is applied. Experimental results show the proposed interface synthesizer functioned correctly in the HW/SW codesign environment.
-
With increasing design complexity, shrinking time-to-market window, and various demands from markets, the traditional design methodologies reach-ed a ceiling. In a search for a way to tackle these problems, novel concepts and methodologies have been proposed in the past years. The paper briefly presents the design issues, and concepts, introduces commercial tools, and finally proposes a conceptual methodology that addresses the issues.
-
In this paper, the animated simulation system (Anisim) is proposed in order to develope an efficient functional system verification tool. It displays the simulation results of the designed system using graphic animation with various models lot the target system. With simple interface definitions given by the user, Anisim generates interface codes automatically. Users can describe and model the target system with the generated interface codes. Since the simulation engine is implemented in C-language, modeling is very simple and simulation can be performed in real time.
-
We have been aware fer some time. that it is becoming harder to develop ASIC only, using the vendor wire model for the current top-down/bottom-up process. Because VDSM has a much bigger wired delay than cell delay, it is also difficult to reduce development time, as well as time-to-market, while developing several million gate ASIC's. The same is true for high frequency ASIC's with VDSM (which have larger wire delay versus cell delay). Therefore, a solution called “RTS-GDS”, using physical constraints fur SOC with timing met, is being actively discussed. This paper suggests a methodology for SOC development by utilizing a top down flow via CWLM along with discussing potential problems. This paper also provides a design flow, including physical synthesis, DFT, floor plan and CWLM, all of which are relevant to proper SOC development.
-
In this paper, we propose a prime code and a new cryptographic algorithm for encryption and decryption as its application. The characteristics of prime numbers with irregular distribution and uniqueness are used to generate the prime code. Based on the prime code, an encryption algorithm for secret key is presented. Since the algorithm requires simpler operations than existing encryption such as DES, the burden for hardware implementation of the encryption and decryption process is alleviated.
-
소형화와 안전성에서 보다 더 진보된 ECC( Elliptic Curve Cryptography) 암호화 알고리즘의 하드웨어적 구현을 제안한다. Basis는 VLSI 구현에 적합한 standard basis이며 m=193 ECC 승산기 회로를 설계하였다. Bit-Parallel 구조를 바탕으로 Digit-Serial/Bit-Parallel 방법으로 구현하였다. 제안된 구조는 VHDL 및 SYNOPSYS로 검증되었다.
-
Data security is an important issue in today's computer networks. In order to construct a safe infra in the open communication network, a cryptography is necessarily applied to several communication application fields like a high-speed networking system supporting real-time operation. A cryptography which has already realized by a software is designed by using a hardware to improve a throughput. In this paper, we design hardware architecture of IDEA by using a single iterative round method to improve a encryption throughput. In addition, we intend to develop a hardware design methodology that a specific cryptography operate with high-speed. The hardware model is described in VHDL and synthesized by the Samsung KG 80 Library in the Synopsys development software tool. With a system clock frequency 20MHz, this hardware permits a data conversion rate of more than 116 Mbit/s.
-
In recent years, security is essential factor of our safe network community. Therefore, data encryption/ decryption technology is improving more and more. Elliptic Curve Cryptosystem proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits lot the same security, there is a net reduction in cost, size, and time. In this paper, we design high speed underlying field arithmetic processor for elliptic curve cryptosystem. The targeting device is VIRTEX V1000FG680 and verified by Xilinx simulator.
-
Oversampling modulators based on high-order sigma-delta modulation provide an effective means of achieving high-resolution A/D conversion in a VLSI technology. Because high-order noise shaping great]y reduces the quantization noise in the signal band. This paper introduces a third-order cascaded sigma-delta modulator that is stable for large input level. Modulator was simulated 3.3V single power supply voltage in 0.65
$\mu\textrm{m}$ CMOS technology. It achieves 80㏈ SNR for a 20㎑ input signal bandwidth. A lock frequency is 3㎒ that is 80 oversampling ratio. -
This paper presents a low-voltage, low-power
$\Sigma$ Δ modulator for audio applications. It use a simple second-order fully-differential switched-capacitor structure with a sampling frequency of 12.5 MHz and oversampling ratio of 256. It operates from a single 1.5V Bower supply and dissipates 2 ㎽. Extensive simulations using 0.25${\mu}{\textrm}{m}$ CMOS Process parameters show that it achieves 96㏈ peak SNDR in a 22 KHz bandwidth. -
In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65
$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance. -
This paper introduces the design of high-speed analog-to-digital converter for hard disk drive (HDD) read channel. This is based on autozero technique for low-error rate, and Double Speed Dual ADC(DSDA) technique lot efficiently increasing the conversion speed of A/D converter. This An is designed by 6bit resolution, 800M sample/s maximum conversion rate, 390㎽ power dissipation, one clock cycle latency in 0.65
$\mu\textrm{m}$ CMOS technology. -
Akers Algorithm has more useful information and technique of undetectable faults for fault simulation. To verify of this algorithm, we have constructed A1, A2 and A3 simulator and surveyed simulation time.
-
In this paper, we address the requirement of VHDL parser for design rule checker, and the structure and implementing method of design rule checker which checks if IP design is valuable to reuse. This checker builds the grammar trees from the design rules, and the internal graphs representation from IP design data. It maps the nodes of the grammar trees and the internal graphs to check if it violates the design rules. The design rule checker can do the cross reference between source codes and error messages to find error position easy.
-
Fault simulation is often necessary to determine the fault coverage of a given test, that is, to find all the faults detected by test. In this paper we implement a deductive fault simulation using counting method. Counting method uses f
$\sub$ i/ of fault table and Search list to compute set operation. f$\sub$ i/ was counted by fault list of input gate. And we propagate fault list from primary inputs toward primary output by comparing with controling sum. It improved performance by reducing search of faults. -
This paper presents a technique used for verifying the design of AE32000, a 32-bit microprocessor core. We follow the commonly used verification procedure while speeding up and completing the debugging process by adopting a reverse engineering scheme.
-
A network is an important portion of communications in these days. Because of many inconveniences of a wired-network, wireless solutions have been studied for many years. One of the results of those efforts is IEEE 802.11, wireless LAN. This paper briefly summarizes wireless LAN and specially focuses on the design of a network processor for the wireless LAN system. The processor has 16-bit instruction set suitably selected for network processing and low-power consumption. It is implemented and verified with a wireless LAN system model. The wireless LAN system is modeled in RTL excluding the RF module. The processor can be used in many wireless systems as a controller and utilized as a test module for the research of low-power schemes.
-
This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.
-
GSM(Global System for Mobile Communication) system which is being used in Europe is composed A3, A5 and A8 algorithms. In this paper we implement A3 algorithm using VHDL, and verify the design by simulation. The A3 algorithm is divided into 3 parts, the encryption part, in which F-function encrypts 64 bit block data;the key generation part, which produces 32 bit subkeys;the control part, which produces the control code.
-
In this paper has studied an enhanced usage parameter control algorithm, which is one of the preventive traffic control method in ATM networks. The proposed algorithm is based on the CLP(Cell Loss Priority) bit in the ATM cell header. This algorithm can eliminate the measurement phasing problem in cell conformance testing in ATM networks. The proposed algorithm can minimize the cell loss ratio of high priority cell(CLP = 0) and resolve the burstiness of eel]s which may be generated in the multiplexing and demultiplexing procedure. For the performance evaluation, we have simulated the proposed algorithm with discrete time input traffic model and the results show that the performance of the proposed algorithm is better than that of ITU-T usage parameter control algorithm.
-
In this paper, we describes the design of a CPU compatible with ARM9 processor. The CPU is fully synthesizable and described in Verilog-XL. Starting from the synthesizable ARM7 compatible CPU we developed earlier, we modified its pipeline to five stages. For this we first partition the behaviors of each instruction into five stage pipeline operations. Then we designed the controller and the datapath considering the forwarding or interlock schemes. Finally the compatibility of the designed CPU is verified by comparing the results of every instruction executed in test programs with those of the reference simulator developed for the ARM7 compatible CPU.
-
Verification is one of the most critical and time-consuming tasks in today's design process. This paper describes the basic idea of Co-verification and the environment setup for the design of DVD Servo with TeakLite DSP core by using Seamless CVE, Hardware/software Co-verification too1.
-
This paper describes the design of a CMOS frequency synthesizer using programmable frequency divider with novel architecture. A novel architecture of programmable divider can be producted all of integer-N and fabricated by 0.65
$\mu\textrm{m}$ 2-poly, 2-metal CMOS technology. Frequency synthesizer is simulated by 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS technology. This circuit has settling time of 1.5${\mu}\textrm{s}$ and power consumption of 70㎽. Operating frequency of the frequency synthesizer is 820MHz∼l㎓ with a 2.5V supply voltage. -
This paper introduces to design analog circuits with Verilog-A. It is a tool for design and simulation of analog ICs in behavioral level. Verilog-A has been already established standard and used to IP development in USA. We have proved the possibility of Verilog-A by comparing with measurement data of a fabricated 235MHz PLL circuit. This paper also describes another advantage of Verilog-A.
-
We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO
$_{3}$ /SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer. -
In this paper, we demonstrated an analytical description method of forward voltage drop and reverse voltage of
$P^{+}N$ junction diode with <111> oriented antimony doped silicon wafer 60keV boron implantation computer simulation results. In order to make electrical activation of implanted carriers, thermal annealing are carried out by RTP method for 1min at$1000^{\circ}C$ inert gas condition. -
InP/lnGaAs HPT's were fabricated by employing Indium Tin Oxide(ITO) transparent emitter contact. The device showed the current gaing 70 was obtained but the emitter series resistance was significantly increased. the electrical charateristics of the device were similar to HBT's. However Vceoff was shifted the positive direction. Such a shift ma be resulted from the formation of the shottky barrier rather than the ohmic contact between ITO and n+ InP emitter.
-
A new time-to-digital converter is designed and the converter is based on a voltage-to-frequency converter and a counter. The converter output is obtained without delay time and the resolution improves with increasing input time interval because the output of voltage-to-frequency converter increases linearly. In the designed circuit the input time intervals range is from 100nsec to 3
${\mu}$ sec. -
It is expected that there will be the regulation for limiting the amount of Hg content in cold cathode fluorescent lamp (CCFL) for LCD backlight system. Now it is necessary to develop mercury-free backlight system. The mercury-free CCFL coated with PDP phosphors was fabricated and evaluated. The CCFL filled with Xe and Ne showed 4500 ㏅/
$m^2$ with efficiency of 13 lm/W. -
To investigate the compact effect of the different area of an active layer and the different type of heatsink on the junction to ambient transient thermal impedance, we have characterized the thermal behavior of power MOSFETs that have three different areas of an active layer and two types of heatsink. To do so, the "cooling curve method" has been used in order to measure the junction-to-ambient transient thermal impedance Zthja that represents the thermal behavior of the devices. The measured data depiets that the larger area of an active layer gives the better-in other words. smaller-thermal impedance, and that the larger size of a heatsink improves the thermal impedance.
-
In this paper, we present a high-performance SiGe HBT's RF input impedance parameter extraction method. The SiGe HBT has emitter width of 0.5
${\mu}{\textrm}{m}$ and length of 6${\mu}{\textrm}{m}$ . S-parameter has been measured with the collector current of 1~3㎃ using on-wafer RF measuring system . The pre-calculation method was used in order to overcome the local minimum problem. This method enabled us to extract a RF(1~10㎓) input impedance parameter. -
A new Smart rower IC's based on the Partial SOI technology was designed for such applications as mobile communication systems, high-speed HDD systems etc. A new methodology of integrating a 0.8
${\mu}{\textrm}{m}$ BiCMOS compatible Smart Power technology, high voltage bipolar device, high speed SAVEN bipolar device, LDD NMOSFET and a new LDMOSFET based on the Partial SOI technology is presented in this paper. The high voltage bipolar device has a breakdown voltage of 40V for the output stage of analog circuit. The optimized Partial SOI LDMOSFET has an off-state breakdown voltage of 75 V and a specific on- resistance of 0.249mΩ.$\textrm{cm}^2$ with the drift region length of 3.5${\mu}{\textrm}{m}$ . The high-speed SAVEN bipolar device shows cut-off frequency of about 21㎓. The simulator DIOS and DESSIS has been used to get these results. -
We report the experimental results for the coupling properties of the an side-polished single-mode fiber covered with metal-clad planar waveguide. The experimental results show that the large birefringence of a metal-clad planar waveguide facilitates the effective separation of TE and TM polarization in the spectral domain. Additionally the resonant wavelengths of the device are tuned based in the thermo-optic effect of polymer planar waveguide.
-
In this paper, a Gm-C filter for low voltage and low power applications using a fully-differential transconductor is presented. The designed transconductor using the series composite transistors and the low voltage composite transistors has wide input range at low supply voltage. A negative resistor load (NRL) technology for high DC gain of the transconductor is employed with a common mode feedback (CMFB). As a design example, the third-order Elliptic lowpass filter is designed. The designed filter is simulated and examined by HSPICE using 0.25
${\mu}{\textrm}{m}$ CMOS n-well parameters. The simulation results show 105MHz cutoff frequency and 2.4㎽ power dissipation with a 2.5V supply voltage. -
Organic light emitting diodes(OLEDs) have been expected to find an application as a new type of display since C. W. Tang and VanSlyke first reported on high performance OLEDs. This paper has been stuied a green organic EL device using dye doped emitting layer such as C6(Coumarin 6). In the Alq-based e]ectroluminescence diodes, we applied highly fluorescent molecular(Coumarin 6) and obtained enhancement in the electroluminescence efficiency.
-
Organic electroluminescent(EL) devices have been expected to be useful in novel-type flat-panel displays. This paper has fabricated and analyzed a red organic EL device with the use of organic dyes, such as DCMI and Nile Red. In this paper, the light emitting layer consists of tris-(8-hydroxyquiniline) aluminum(Alq
$_3$ ) doped with organic dyes. -
In this paper, we was fabricated and analyzed a blue organic electroluminescent devices with the organic dye, such as 1,1,4,4-Tetraphenyl-1,3-butadi-ene(TPB). The device was made by simultaneously co-depositing two materials. The device structure was composed of the ITO glass, TPD, Alq
$_3$ doped TPB, and aluminum(A1) electrode. Carrier injection from the two electrodes was significant]y observed and the blue light in EL spectrum, with an emission maximum at 462nm, was triggered at a driving voltage of 11V. -
Recently, Turbo code has been considered for channel coding in IMT-2000(International Mobile Telecommunication-2000) system, because it offers better error correcting capability than the traditional convolution/viterbi coding . In this paper, a turbo code decoder for speech transmission in IMT-2000 system with frame size 192 bits, constrait length K=3, generator polynomials G(5,7) and code rate R=1/3 is designed using SOVA(Soft Output Viterbi Algorithm) and block interleaver
-
In this paper, we designed a turbo decoder using VHDL. To maximize effective free distance of the turbo code, we implemented pseudo random interleaver. A MAP(Maximum a posteriori) decoder is used as a primimary decoder. We avoided multiplication by using lookup tables(ROM). We expect that this small-sized turbo decoder is suitable for mobile communication. We simulated turbo decoder with Altera MAX+PLUS II.
-
This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.
-
In this paper, we propose a Reed-Solomon decoder for the DVD Reed-Solomon(RS) product code based on new efficient euclid cell architecture suitable for Modified Euclid Algorithm. We synthesized the RS decoder using Hyundai 0.65um CMOS standard cell library and compared the performance of the decoder with one of the conventional architectures. The result shows that the proposed euclid cell use about 32% less symbol time.
-
This paper proposes a new FIR fillet architecture for the spectral shaping filter used in the transmitter and the receiver for QAM-VDSL modem. This architecture reduced the hardware property and the power consumption. We derive algorithms for reducing the number of multipliers and the memory architecture for reducing the power consumption. The proposed filter has been implemented using VHDL and performed functional simulation.
-
In this paper, we designed a 192-tap echo canceller for a modem using VHDL. To evaluate errors, we used adaptive algorithm. We adopted pipeline technique and realized delay-taps with RAMs. We simulated this design using Altera MAX+PLUS II.
-
This paper proposes a high-speed and area-efficient FFT algorithm and performs a hardware implementation. This algorithm, named by “Radix-4/2”, uses the feature of existing radix-2
$^3$ algorithm, It reduces the number of non-trivial multipliers in SFG to the ratio of 3 to 2 campared with radix-2 or radix-4 algorithm and radix-4/2 has also twice throughput as radix-2$^3$ algorithm's. It is proved that FFT processor using the proposed algorithm and 64-point MDC pipeline architecture has twice throughput as radix-2$^3$ algorithm's, and reduces areas by 25 percentages in contrast to radix-4 algorithm's. -
In this paper, we designed a 256-point FFT processor using VHDL. We adopted Radix-2
$^2$ SDC(Single-path Delay Commutator) architectures to reduce the number of complex multipliers. We confirmed the operation of the design through simulation using Altera MAX+PLUS II. -
In this paper, the 7
${\times}$ 7 MMI Multiplexer is designed. The 1${\times}$ 7 Splitter and the 7${\times}$ 7 Coupler are designed and the phase-matched away length is determined. Then this result is confirmed by the simulation considering the intermode coupling. The MMI Multiplexer has The 14nm operating wavelength region, the 2nm wavelength spacing and the 1${\times}$ 3$\textrm{mm}^2$ size. -
In this paper, The Influence of chromatic fiber dispersion on the transmission distance of MMW(millimeter-wave) link is analyzed and discussed. It is shown that dispersion significantly limits the transmission distance in intensity modulated direct detection and heterodyne links operating in the above 20㎓ frequency region by inducing a carrier to noise penalty on the transmitted signal. We analyze and discuss the influence of dispersion induced CNR(Carrier to Noise Ratio) penalty for direct detection and heterodyne method from simulation.
-
Concentric-Circle-Grating (CCG) cavity is analyzed by coupled mode theory. In this case concentric grating is acting as both feedback element and output coupler. In our calculations radiation loss terms are included in guided coupled mode equations. The surface-emitted field distribution is obtained in self-consistent manner.
-
We have calculated the optimum refractive index and thickness for a single layer antireflection coating as a function of active layer width and thickness in buried channel waveguides. The results using the variational method to obtain the field profiles are compared to those using the effective index method.
-
In this paper, we proposed a new visual cryptography scheme based on optical interference which improves the contrast and SNR of reconstructed images comparing with conventional visual cryptography method. We divided an binary image to be encrypted into n slides. To encrypt them, (n-1) random independent keys and one another random key by XOR process between four random keys were prepared. XOR between each divided image and each random key makes encrypted n encrypted images. From these images, encrypted binary phase masks can be made. For decryption all of phase masks should be placed together in the interferometer such as Mach-Zehnder interferometer.
-
The control of the data retention time is a main issue for realizing future high density dynamic random access memory. In this paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced
$\Delta$ Rp increase using buffered N- implantation with tilt and 4X-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N- concentration which is intentionally caused by Ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. -
This paper proposed resource allocation algorithm for the minimum power consumption of functional unit in high level synthesis process as like DSP which is circuit to give many functional unit. In this paper, the proposed method though high level simulation find switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To used the switching activity find the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step.
-
Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.
-
In this paper, we put forth a procedure that target low power logic synthesis based on XOR representation of Boolean functions, and the results of synthesis procedure are a multi-level XOR form with minimum switching activity. Specialty, this paper show a method to extract the common cubes or kernels by Boolean matrix and rectangle covering, and to estimate the power consumption in terms of the extracted common sub-functions.
-
Several new via structures in printed circuit boards are proposed, fabricated and characterized in RF regime. The new structure with a larger inductance component in the bottom layer shows 3㏈ improvement over the conventional structure. The ADS simulation with model parameters extracted from 3D fie]d solver matches with the characterization of these vias
-
In this paper, We described the procedures to generate an input-output buffer information specification (IBIS) model in digital IC circuits. We gives the method to describe IBIS standard I/O for the characteristics of I/O buffer and to represent its electrical characteristics. The parameters of I/O structure for I/O buffer modelling are also referred, and an IBIS model for CMOS, TTL IC, ROM and RAM constructed amounts about 216. This IBIS model can be used to the simulation of signal integrity of high speed circuits in a PCB level.
-
In this paper, a SIMD 64bit MAC (Multiply -Accumulate) unit is designed. It is composed of two 32bit MAC unit which supports SIMD 16bit operations. As a result, It can process two 32bit MAC operations or four 16bit operations in one cycle. Proposed MAC unit is described in Verilog HDL. After functional verification is performed, MAC unit is synthesized and optimized with 0.35
$\mu\textrm{m}$ standard cell library. The synthesis result shows that this MAC unit can operate at 80㎒ of clock frequency in 85$^{\circ}C$ , 3.0V, worst case process and 125㎒ of clock frequency at 25$^{\circ}C$ , 3.3V, typical case process. It achieves 320Mops of performance, and is suitable for embedded DSP processors. -
In this paper, a high-performance and small-area floating-point divider, which is suitable for embedded processors and supports all rounding modes defined by IEEE 754 standard, is designed using the series expansion algorithm. This divider shares and fully utilizes the two MAC units for quadratical convergence to the correct quotient. The area increase of two MAC units due to the division is minimized in this design, so that it can be suitable for embedded processors. The tested HDL codes are synthesized and optimized with 0.35
$\mu\textrm{m}$ CMOS standard celt libraries. The results show that the latency of the synthesized divider is 17.43 ㎱ in worst condition. But, the divider calculates the correct rounded quotient through only 6 cycles. -
In this paper, we designed 32-Hit MAC architecture of a RISC Processor for portable terminals such as cellular telephones, personal digital assistants, notebooks, etc. In order to have minimum area with best performance, the MAC performs 32 by 8 multiplication per cycle, with early termination circuit that enables multiply cycles depend on the value of multiplier. It uses the sign bit of a partial product and two extra bits for sign extension, The MAC is modeled and simulated in RTL using VHDL. The MAC is synthesized using IDEC C-631 Cell library based on 0.6
$\mu\textrm{m}$ CMOS 1-Poly 3-metal CMOS technology.