In this paper, a specification for wireless LAN MODEM using direct sequence spread spectrum (DS/SS) technique is presented. Some algorithms and hardware architectures for an efficient implementation of the DS/SS MODEM are suggested. In the method, all baseband signal processing are done digitally for single chip implementation. Schemes of DQPSK baseband modulation/demodulation, despreading with digital matched filter, digital timing recovery, and efficient carrier sensing are among the discussed algorithms. We also performed various kinds of simulations to evaluate the system performance and to extract parameters for hardware implementation. In addition, the pictorial view of ASIC of the SS MODEM is also shown.

The main contribution of this paper can be summarized in two items as follws. Firstly, a modelling of mobile communication channel with Rayleigh fading characteristics is presented. Actual signal environments can be approximated as being real measurements by a proper mathematical representation of fluctuation of channel parameters due to Doppler effect, that is determined by the relative speed between transmitter and receiver, and noises, that vary at each sampling time. Secondly, an alternative procedure of synthesizing an adaptive equalizers is presented for recovering original signals that have been corrupted through the modelled channel. In order to compute the optimal tap coefficients for a high speed data(512 k symbol/sec) on a real-time basis, the CGM that guarantees fast and stable convergency is adopted during the training period of each frame. The coefficients obtained by the CGM are used as initial values for the LMS algorithm to trace the optimal coefficients during the data period that vary at each sampling time due to the mobility and noise at the receiver. Using the modelling presented in this paper, distributions of received signal power in various signal environments are demonstrated. The performance of the eqalizer proposed in this paper is shown as a function of BER under the various signal circumstances of mobile communications.

Bo-Back-N ARQ is widely used in packet networks for error and flow control methanisms. This paper analyzes the network throughput under the go-back-N schem. Contrast to other analytic methods which assume independent frame losses or the first order Markov frame analytic methods which assume independent frame losses or the first order Markov frame losses concoptually, the proposed method takes into account the correlation between successive frame losses in a congested node. Computer simulation shows that our method generates more accurate performance results that independent assumption method. We apply the proposed method to analyze the performance of BWM in high speed networs. Our results show that BWM maintains the independence between traffic streams.

For a parabolic reflector antenna, a simple method is presented for computing efficiently the average power pattern degradations caused by the surface roughness of the reflector and misalignments between the reflector and the feed. In this procedure, both nonuniform surface errors and nonuniform illuminations are employed. The assumptions to derive the expressions are that in each annular region of the antenna, the rms value of the surface roughness is known, and in a zone in a annular region, the phase error by misalignments is constant, and can be taken to its value at the center of the zone. Detailed parametric studies are performed with derived expressions to determine the effects of those errors and illumination tapers on parameters such as gain and sidelobe levels.

A new Kirchhoff approximation(KA) method was proposed for microwave scttering from randomly rough surfaces. Using the spectral representation of delta function and its sifting theorem, a new KA was formulated directly without any further approximation, and this formulated was used to compute exact backscttering coefficients. The validity of the KA was verified by a numerical method, and this new KA technique was used to evaluate the existing approximated KkA methods; i.t., the zeroth-order and the first-order approximated physical optics(PO) models. It was shown that the first-order approximated PO model has small error than the zeroth-order approximated PO model at low incidence angles and the opposite happens at higher incidence angles. This new KA model can be used to compute exact scattering coefficients in the validity regions of KA and to evaluate other theoretical and numerical models for scattering from randomly rough surfaces.

The aims of this study are to evaluate the measurement capability of the electromagnetic power and to understand the current state of standard maintanance of the eight participants among the thirteen national calibration and test organizations. The calibration factors were measured at six test frequencies, 50, 100, 500, 1000, 5000, 10000 MHz by organizations and KRISS on the basis of round robin test. The results were analyzed by calculating the standard deviation of the measured values from the standard values. The analysis shows good agreement within 1.0% for all participants at the measurement frequencies. Therefore, the measurement capability of all participants is good in the frequency range of 50 MHz to 10 GHz. For the four participants which specified standard deviations of repeated measurements in their reporst, the total uncertainties is less than 1.9% at the measurement frequencies.

a numerical method to the problem of mutual admittance between two slots is considered by use of conservation of complex power. Calculation of mutual admittance is compared with other results. And mutual admittance obtained by the method is used in the analysis for the broadband rectangular microstrip antenna geometry using E0plane gap coupling. The theoretical results for both return loss and radiation pattern of the broadband antenna are compared with experimental results. Good agreement between calculated and measured values has been observed.

In order to implement broadband RAM's(Radar Absorbing Materials) made up of multiple dielectricl layers, the design variables such as the dielectrci constaints, the depths and the loss tangents of dielectric are optimized. The wave impedances regarding the reflective wave are found in dielectrics, input impedances and reflection coefficients with multiple dielectric layers are derived from the transmission line circuit theory. Finally, minimum average reflective power and optimum design variables are obtained by applying the numerical technique, called modified Powell method. In case of four dielectric layers with inequality constraints in design variables, a quite favourable and feasible result with the total depth of 1.1 cm, the average reflective power of 0.85% over the bradband frequency range is obtained for a specific example.

A subreflector of an offset dual reflecor antenna system mounted on satelite is analyzed by Uniform Geometrical Theory of Diffraction(UTD). In order to get the total electric field at an observation point, the reflected field and the diffracted fields obtained by UTD are summed. The reflected point and the diffracted points which have to satisfy nonlinear equations are obtained by numerical methods. The numerical results show taht diffracted fields eliminate the discontinuity of reflected fields at the shadow boundary. To show the validity of our results, the field pattern of the symmetric hyperboloidal reflector is computed and compared with S. W. Lee et al.'s results. At various obsevation angles, radiation patterns of offset ellipsoidal subreflectors offseted by a circular corn and by an elliptic corn are obrained, repectivelly.

Lateral p-i-n photodiodes have been fabricated, electrically tested, and incorporated into microwave control circuits such as an optically excited microwave atttenuator and reflection type phase shifter. Circuit design procedures for the loaded-line phase shifter with the optically controlled p-i-n photodiode are presented. The equal loss loading mode presented for the first time for the phase shifter circuits with lossy load allows an equal insertion loss of the phase shifter in both of its phase states. It is found that the insertion loss of the equal loss loading mode phase shifter constructed with the fabricated p-i-n photodiode load are about 3dB for 11.25$^{\circ}$ bit and 1dB for 5.625$^{\circ}$ bit for the frequency range of 2GHz to 11GHz.

The ferromagnetic resonance properties of Mg ferrites which have various porosity grain size, and saturation magnetization are measured at one frequency. This allows a determination of the anisotropy field(Ha). The saturation magnetization multiplied by porosity is the resonance magnetic field. As the saturation magnetization increases, the linewidth decerases due to decrement of magnetic inhomogenity in sample. the porosity is a major factor broadening the linewidth for Mg ferrite when porosity is more thatn 6%, and the anisotropy field is dominant when porosity is less than 6%.

Trench-Gate SOI LIGBT with improved latch-up capability has been proposed and verified by MEDICI simulation. The new SOI LIGBT exhibits 6 time larger latch-up capability of the new device is almost preserved independent of lifetime. the large latch-up capability of the new SOI LIGBT may be realized due to the fact that the hole current in the new device would bypass through the shorted cathode contact without passing the p-well region under the n+ cathode. Forward voltage drop is increased by 25% when a epi thickness is 6$\mu$m. However, the increase of the forward voltage is negligible when the epi thickness is increased to 10$\mu$m. It is found that the swithcing time of the new device is almost equal to the conventional devices. Evaluated breakdown voltage of proposed SOILIGBT is 250 V and that of the conventional SOI LIGBT is 240 V, where the thickness of the vuried oxide and n- epi is 3$\mu$m and 6$\mu$m, respectively.

The three-dimentional effects on the breakdown voltage of non-reachthrough planar junctions which have the finite lateral radius of window curvature are analytically investigated. The critical electric fields at breakdown and the breakdown voltages are expressed successfully in a form which is normalized to the parallel plane case. The analytical results are in excellent agreement with the published results of experiment and the quasi-three-dimensional device simulation by MEDICI for non-reachthrough plane junctions having different background doping and junction depth. The results may be applicable to the estimations of breakdown voltages in many practical power devices.

We report hybrid and passive mode-locking results of tilted-stripe AlGaAs semiconductor laser traveling wave amplifiers with saturable absorbers. Dependence ofthe pulse width on the mode locking frequency, the bandwidth of spectral filters, and the bias current of the laser amplifier are investigated. We generate 4 ps optical pulses by using the hybrid mode locking technique. The repetition rate and the peak power of generated pulses are 516 MHz and 170 mW, respectively. The tuning range of uor mode locked laser is 10 nm with the center wavelength of 780 nm. We also generate 2.6 ps optical pulses with peak power of 830 mW by using the passive mode locking technique.

AlGaAs/GaAs HBTs have been fabricated using SABM (Self-Aligned Base Metal) process technique. The mesa type HBTs were fabricated through following steps: isolation implant, wet etching, metal lift-off, and airbridge interconnection process. The fabricated HBTs with 2umx10um size emitter showed a common emitter current gain of 10 at a collector current density of Jk=100kA/cm$^{2}$, a breakdown volgate BVCEO of 8V, and the ideality factors of base and collector junctions of 1.6 and 1.1, respectively. On-wafer S-Parameter measurement at 0.5~18GHz has been made for the characterization of the common emitter HBTx with a 2umx10um size emitter. The extrapolated current gain cut-off frequency of ft=30GHz and maximum oscillation frequency of fmax=23 GHz were obtained at a collector current density of Jc=70kA/cm$^{2}$. Small signal HBT equivalent circuit was extracted from the S-Parameter data.

The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

We have studied the fabrication self aligned atmospheric pressure(AP) CVD a-Si thin film transistor with source-drain ohmic contact by using ion shower doping method. The conductivity is 6*10$^{-2}$S/cm when the acceleration voltage, doping time and doping temperature are 6kV, 90s and 350.deg. C, respectively. We obtained the field effect mobility of 1.3cm$^{2}$/Vs and the threshold voltage of 7V.

Eteching characteristics of the Indium Tin Oxide (ITO), which is transparent conductor, was investigated with CH4/H2 and Ar as etching gases for the Reactive Ion Etching (RIE). With CH4/H2 for the etching gas, the highly selective etching characteristics for the ITO on GaAs was obtained. It was examined that the dominant etching parameter for the selective etchning of ITO on GaAs structure was the chamber pressure. But, the etching selectivity for ITO on InP was poor eventhough we tried systematic etching. RIE etching conditins using CH4/H2 gas was limited due to the formation of polymer on the substrates. In the case of Ar gas for the reactive gas, the selectivity of ITO on BaTiO3 was above 10. The etch rete of ITO was more sensitive to the etching parameters than that of BaTiO3, which was almost constant with different etching parameters.

A double-heterostructure mesa-stripe-geometry laser diode integrated with thermoelectric Peltier cooler has been designed and fabricated. Epi-layers have been grown by metal organic chemical vapor deposition(MOCVD) method. Peltier cooling effect has been measured for devices with a mesa width of 14$\mu$m and a cavity length of 380$\mu$m. The effects of thermoelectric cooling could be shown by measuring the optical output of the laser with the increase of the current in the thermoelectric cooler. While the input courrent of the laser was maintained at 250mA, the optical output was decreased from 4.8mW to 3.8mW due to heating, but with the thermoelectric cooler on the optical output power was recovered by more than 40%. The results show that the complicated cooling device is not needed since the cooling can be achevied by the developement of the fabrication processing.

An accurate threshold voltage extraction scheme for MOS transistors is presented. In contrast to alternative methods recently reported in the literature, this scheme does not need matched replica of the transistor under test, and thus can be applied more effectively and accurately to raal-time on-chip applications where threshold voltage measurements are required for many transistors with various geometries and bias conditions. The proposed scheme is accurately implemented in a matching-free way using a ratio-indepentent switched-capacitor subtracting amplifier and a dynamic current mirror. Nonideal effects associated with these circuits have been investiggated and compensated.

Phosphorous was deped in silicon thin films by Ion Mass Doping and Changes in the electrical resistance with respect tko heat treatments were investigated. SOI(Silicon On Insulator) thin films which contain few grain boundaries prepared by ZMR(Zone Melting Recrystallization) of polysilicon films, polysilicon films which have about 1500 $A^{\rarw}$ of grain size prepared by LPCVD at 625.deg. C, and amorphous silicon thin films prepared by LPCVD at low temperature were used as substrates and thermal behavior of phosphorous after RTA(Rapid Thermal Annealing) and furnace annealing was carefully studied. Amorphous thin films showed about 10$^{6}$ .OMEGA./ㅁbefore any heat treatment, while polycrystalline and SOI films about 10$^{3}$.OMEGA./¤. All these films, however, showed about 10.OMEGA./ㅁafter furnace annealing at 700.deg. C for 3hrs and RTA showed about the same trend. Films with grain boundaries showed a certain range of heat treatment which rendered increase of the electrical resistance upon annealing, which could not be observed in amorphous films and segregation of doped phosphorous by diffusion with annealing was thought to be responsible for this abnormal behavior.

In this study, very fine photoresist pattern was examined using the image reversal process. And very fine photoriesist pattern (less than 0.2um) was obtsined by optimizing the exposure and reversal baking condition of photoresist. The produced pattern does not show the loss of thickness, and has a sparp negative edge profile. also, the ion implanted 0.25um T-shaped gate MESFET was fabricated using this resist pattern and the directional evaporation of gate metal. The fabricated MESFET has the maximum transconductance of 302 mS/mm, and the threshold voltage of -1.8V, and the drain saturation current of this MESFET was 191 mA/mm.

A novel imaging method in which time-division spinning reticle samples different pixel location of input image in different time is presented. The lens collects the beam passing throughthe reticle to a photodetector. Image reconstruction is accomplished by sampling the detector output corresponding to the spinning speed of reticle. Since the time-division reticle system removed the necessity of bandpass filter bank which has sharp cut-off characteristic, high resolution image is obtained without increasing the number of filter. To confirm the validity of this method, a computer simulation and an optical experiment using visual light are presented.

The 1st and 2nd-order grating structure for long wavelength DFB(Distributed FeedBack) laser diodes are successfully fabricated on InP substrates by using electron beam lithography and reactive ion etch techniques, and also characterized non-destructively by diffraction analysis without removal of photo-resis layer. A new composite layer made by lifted-off Cr layer on thin SiO2 film is developed and used as an etch mask, because PMMA, the e-beamresist, is unsuitable for reactive ion etch of InP. In addition, it is experimentally confiremed that diffraction analysis makes it possible to predict the grating parameters, and the analysis can be used as a non-destructive on-line test to prevent incomplete gratings from being successively processed.

Metal-Metal Matrix(M$^{3}$) layout is a recently proposed layout style which uses minimum amount of poly wires for high speed operation. In this paper we propose a method of generating functional modules in M$^{3}$ layout style. In the proposed method the transistors and the input/output lines of the given circuit are first placed in M$^{3}$ layout style and then they are interconnected using two metal layers. We develop a new placement method by simulated annealing, and we modify the well known channel routing method for the interconnections. When we applied our method to several logic circuits, the area of the generated layout is smaller than the ones by the previously known method. Our results also compares favorably to the other layout styles like gate matrix layout.

For effective module generation, a detailed router which can handle complicated routing regions on multimple layers of interconnection under various constraints is necessary. In this paper, a new improved maze routing technique is described, which can find the shortest path for each net without allowing stacked vias. In this method, two cost values are stored at each grid point. The cost values represent the routing costs from the terminal of the net being routed to the grid point. One cost value shows the cost of the shortest path without making a via at the grid point and the other cost value shows that with making a via at the grid point. This is the first systematic maze routing technique which can find the shortest path without via-stacking.

An arry circuit is designed for parallel computation of vector-radix 2-D discrete cosine transform (VR-FCT) which is a fast algorithm of DCT. By using a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently implemented with high condurrency and local communication geometry. The proposed implementation features architectural medularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. The array core for (8$\times$8) 2-D DCT, which is designed usign ISRC 1.5.mu.m N-Well CMOS technology, consists of 64 PEs arranged in (8$\times$8) 2-D array and contains about 98,000 transistors on an area of 138mm$^{2}$. From simulation results, it is estimated that (8$\times$8) 2-D DCT can be computed in about 0.88 .mu.sec at 50 MHz clock frequency, resulting in the throughput rate of about 72${\times}10^[6}$ pixels per second.