The structures of inductive irises are used commonly in waveguide filter, especially at highter frequencyies, due to low loss and high temperature stability. However, the iris thickness can not be neglected, as it could be at the lower frequencies. Approximate models assuming zero thickness fail to predict the exact behavior of the filter. And current thickness correction is introduced which is valid in the case of thick irises only. Account of the effect of round is normally not taken. So the necessity of finding a relation for the two factors-iris thickness and round-arises in the design of waveguide filters. This paper describes a mutual relation that considers the combined effect of finite thickness and round from the start. In order to test the validity of the changed relation, weveral examples are given. And the measured response of each case is then compared with the predicted reponse. And it is shown that the radius is of perceptible influence on the transmission coefficient through a thick iris.

Diffraction patterns of the electromagnetic field scattered by a circular cylindrical cavity embedded in a dielectric medium are analyzed. When the wavelength of the incident wave is comparable to the radius of the cavity, strong double dips occur at the locations corresponding to the top and the bottom of the cavity. Furthermore, the phase changes abruptly about the dip points. The changes of the amplitude and the phase patterns are observed as the measuring distance and the signal frequency varies. The effects of the change of the medium dielectric constant on the diffraction pattern is also presented.

In this paper, measured iris transmission loss data and simulated data by using 3-dimension full-wave analysis S/W are presented and compared with Marcuvitz's theory. And by using measured iris data, dual-mode narrow-band channel filters can be successfully implemented. This paper shows that there is severe difference between the transmission loss of iris calculated by using Marcuvitz's equation to calculate iris dimension, if the length of slot iris is longer than .lambda./.pi., and in the long urn the response of channel filter is distorted. Experimental result shows that the characteristic response of implemented channel filter by using the iris transmission loss graph presented here matches well the design specfications. In conclusion, iris transmission loss measurement method will be very useful to design channel filter.

A state-of-the-arts GaAs power metal semiconductor field effect transistor (MESFET) for 3.3V operation digital hand-held phone at 900 MHz has been developed for the first time, The FET was fabricated using a low-high doped structures grown by molecular beam epitaxy (MBE). The fabricated MESFETs with a gate width of 16 mm and a gate length of 0.8 .mu.m shows a saturated drain current (Idss) of 4.2A and a transconductance (Gm) of around 1700mS at a gate bias of -2.1V, corresponding to 10% Idss. The gate-to-drain breakdown voltage is measured to be 28 V. The rf characteristics of the MESFET tested at a drain bias of 3.3 V and a frequencyof 900 MHz are the output power of 32.3 dBm, the power added efficiency of 68%, and the third-ordr intercept point of 49.5 dBm. The power MESFET developed in this work is expected to be useful as a power amplifying device for digital hand-held phone because the high linear gain can deliver a high power added efficiency in the linear operation region of output power and the high third-order intercept point can reduce the third-order inter modulation.

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si cosumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the cosumed Si source during Ti silicidation. This method was applied to the actual fabrication of PMOSFET through SES (selectricely etched Si) techology.

The hot electron induced effective channel length modulation (${\Delta}L_{H}$) and HEIP characteristics in PMOSFET's after bidirectional stress are presented. Trapped electron charges in gate oxide and lateral field are calculated from the gate current model, and ${\Delta}L_{H}$(${\Delta}L_{HD},\;{\Delta}L_{HS}$) is calculated using trapped electron charges and lateral field. It has been found that ${\Delta}I_{d}$and ${\Delta}L_{H}$ are more affected by the stress order (Forward-Reverse of Reverse or Reverse-Forward) than the stress direction, and they vary logarithmically with the stress time. In contrast, ${\Delta}V_{t}$ and ${\Delta}V_{pt}$ are more affected by the stress direction thatn the stress order. The correlation between ${\Delta}V_{pt}$ and the stress time can be explanined as the following polynomial functin: ${\Delta}V_{pt}$=AT$^{n}$. It has also been shown that PMOSFET degradation is related with the gate current and the effects of ${\Delta}V_{pt}$ is the most significant.

This paper proposes the step-stress type-I censoring model for analyzing the data of accelerated life test and reducing the time of accelerated life test. In order to obtain the data of accelerated life test, the step-stress accelerated life test was run with voltage stress to CMOS Hex Buffer. The Weibull distribution, the Inverse-power-law model and Maximum likelihood method were used. The iterative procedure using modified-quasi-linearization method is applied to solve the nonlinear equation. The proposed Weibull step-stress type-I censoring model exactly estimases the life time of units, while reducting the time of accelerated life test and the equipments of test.

InGaAsP/InP uncooled LDs emitting at 1.3$\mu$m wavelength are of interest for several application of fiber-to-the-home, optical interconnection, long-haul high-bit-rate optical transmission systems, etc. The strain compensated PBH-MQW-LD employing 1.4% compressive strained well (${\lambda}=1.3{\mu}m$) and 0.7% tensile strained barrier (${\lambda}=1.12{\mu}m$) layers grown by low pressure metallicorganic vapor phase epitaxy was found to be low threshold current and stable temperature characteristics. The average threshold current of 5.6mA and average slope efficiency of 0.27mW/mA at room temperature were obtained for uncoated uncooled-LD.

We proposed SAW (Self-Algined Selectively Grown W-Gate) MOSFET structure, and strudied electrical characteristics of the fabricated SAW MOSFETs. The threshold volgate of 0.21${\mu}$m SAW NMOSFET was 0.18 V and that of 0.24 ${\mu}$m SAW PMOSFET was -0.16 V. The subthreshold slope was 74 mV/decade for NMOSFET and 82 mV/decade for PMOSFET. The maximum transconductance of NMOSFET and PMOSFET, at V$_{GS}$=2.5 V and V$_{DS}$=1.5 V, were260 mS/mm and 122 mS/mm. The measured saturation drain current at V$_{GS}$=V$_{DS}$ =2.5 V was 0.574 mA/${\mu}$m for NMOSFET and -0.228 mA/${\mu}$m for PMOSFET. The gate resistance of SAW MOSFET was about m$\Omega$cm and the n+-p junction capacitance of SAW MOSFET was about 10% lowas than that of the conventional MOSFET's.

This paper presents the design of a performance-driven interconnect allocation algorithm. The algorithm is based on the idea that the clock period can be minimized by balancing the load for each of the communication paths following specific hardware modules. By performing load balancing for only the communication lines on ciritical paths, the proposed algorithm generates interconnection structures with minimum delays. This approach also shows run time efficiency. Experimental results confirm the effectiveness of the algorithm by constructing the interconnection structures such that the clock period can be minimized for several benchmark circuits available from the literature.

In this paper, an effective method for the minimization of two-level Reed-muller expressions by cube selection whcih considers functional complexity is presented. In contrast to the previous methods which use Xlinking operations to join two cubes for minimizatio, the cube selection method tries to select cubes one at a time until they cover the ON-set of the given function. This method works for most benchmark circuits, but for parity-type functions it shows power performance. To solve this problem, a cost function which computes the functional complexity instead of only the size of ON-set of the function is used. Therefore the optimization is performed considering how the trun minterms are grouped together so that they can be realized by only a small number of cubes. In other words, it considers how the function is changed and how the change affects the next optimization step. Experimental results shows better performance in many cases including parity-type functions compared to pervious results.

We implement the E-plane T-juncition manifold mutiplexer having low insertion loss for output multiplexer of Ku-band satellite transponder. Manifold multiplexer implemented here is composed of 2 channel filters, T-junctions, half-wave waveguide connecting channel filters and manifold, and manifold itself.[1-4] Considering the mass and volume of the satellite transponder, the channel filters are designed to dual-mode.[5-13] And Elliptic filter function is used, which has good characteristics of suppressing the interference between 2 channels. Since the performance of manifold multiplexer depends on the manifold waveguide transmission line length, it's necessary proper analysis. In this paper, we do optimization process of T-junction and other elements by using CAD and implement the manifold multiplexer. An experiment shows that characteristic response of multiplexer matches wel its modeling result.