In this paper, we introduce the nonlinear combiner structure which improves linear complexity and randomness properties on maximum length sequences generated by LFSR. Choosing the primitive polynomial over GF(2S04T) as feedback tap polynomial, we devise nonlinear combiner structure and analyze the random output sequences generated by LFSR with nonlinear function.

In this paper, the directional coupler for Ku-band, which is designed is of the crossguide type with a coupling value of about 3-dB. The apertures chosen for this design are crosses. We used polynomial approximations of rounded end slot to obtain the electric and magnetic polarizability of crossed-slot and compared the results with Cohn's experimental results. The optimized dimensions and positions of the cross aperture are obtained by a trial-and-error reiteration of the program. This paper presents the measurement results for the designed coupler. The very flat coupling shows a total variation of only 29.80$\pm$0.04dB for the design frequency ranges of 12.25GHz-12.75GHz. The measured minimum directivity is 25dB. The aperture attenuation for the finite diaphragm thickness is about 2dB pr 0.5mm, which is in agreement with the theoretical value. The transmission loss and input return loss at center frequency are 0.0564dB and 48.16dB respectively. We obtained the measured minimum directivity of the coupler. Whose apertures are both circles is better than that containing holes in the performance of directivity.

The prediction of crosstalk in one of important problems in estimating the EMC of a system for high speed digital signal transmission. Crosstalk curves are shown in terms of characteristic impedance of lines spacing between lines and rise time of pulse by using general multiple coupled transmission line equation and harmonic-balance method. The coupled symmetrical two-line on dielectric material epoxy-glass FR 4(${\varepsilon}_r$), is fabricated to measure crosstalk occuring at the near end and far end of the passive line. The inter-line is inserted to reduce crosstalk between two microstrip lines. The simulation results and the measurement results are shown and found to be very close.

Optical adders using a modified signed-digit(MSD) number system have been proposed to restrict the carry propagation chain encountered in a conventional binary adder to two positions to the left. But, MSD number system must encode three different states to represent the three possible digits of MSD. In this paper, we propose the design of an optical adder based on 1-bit addition rules by using the method of symbolic substitution (SS). We show that this adder can use binary input which is used by a digital computer, as it is and be implemented by smaller system in size than MSD adder.

We studied threshold voltages and I-V characteristics. considering short channel effect of the fully depleted thin film n-channel SOI MOSFET. We presented a charge sharing model when the back surface of short channel shows accumulation depletion and inversion state respectively. A degree of charge sharing can be compared according to each of back-surface conditions. Mobility is not assumed as constant and besides bulk mobility both the mobility defined by acoustic phonon scattering and the mobility by surface roughness scattering are taken into consideration. I-V characteristics is then implemented by the mobility including vertical and parallel electric field. kThe validity of the model is proved with the 2-dimensional device simulation (MEDICI) and experimental results. The threshold voltage and charge sharing region controlled by source or drain reduced with increasing back gate voltage. The mobility is dependent upon scattering effect and electric field. so it has a strong influence on I-V characteristics.

DC and AC current crowding effects for microwave and high speed bipolar transistors are investigated in detail using a new and accurate measurement technique based on Z-parameter equationa. Using the new measurement technique dc and ac current crowding effects have been explained clearly in bipolar junction transistors. To model ac crowding effects a capacitive element defined as base capacitance (C$_b$), called ac crowding capacitance is added to base resistance in parallel thereby treating the base resistance(R$_b$) as base impedance Z$_b$. It is shown that base resistance decreases with increasing collector current due to dc current crowding and approaches to a certain limited value at high collector current due to current crowding and approaches to a certain limited value at high collector currents regardless of the emitter size. It is also observed that due to ac current crowding base capacitance increases with increasing collector current. To quantigy the ac crowding effects for SPICE circuit simulation the base capacitance(C$_b$) including the base depletion and diffusion components has been modeled with an analytical expression form.

Intermetallic dielectric layer was formed by using SiO$_2$/SOG/SiO$_2$ for aluminum based dual-metal interconnection process and its electric characteristics were evaluated. The dielectric layer was in the cost and facility point of view more useful than the insulator that was formed by etch-back process. The planarity by using SOG process was about 40% higher than that of the insulator by the CVD process. When SiO$_2$ films were deposited by the PECVD process the Al hillock formation during the next process was restrained bucause the intermetalic insulator was made at low temperature. The leakage current was 1${\times}10^{7}~1{\times}10^{-8}A/cm^{2}$ at the electric field of 10$^{5}$V/cm and breakdown filed was 4.5${\times}10^{6}~7{\times}10^{6}A/cm$. So we had confirmed that siloxane SOG was very useful for intermetallic layer material.

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

In this paper semi empirical models are presented for the hot electron induced threshold voltage shift(${\Delta}V_{t}$) and effective channel shortening length (${\Delta}L_{H}$) in degraded PMOSFET. Trapped electron charges in gate oxide are calculated from the well known gate current model and ΔLS1HT is calculated by using trapped electron charges. (${\Delta}L_{H}$) is a function of gate stress voltage such as threshold voltage shift and degradation of drain current. From the correlation between (${\Delta}L_{H}$) has a logarithmic function of stress time. From the measured results, (${\Delta}V_{t}$) and (${\Delta}L_{H}$) are function of initial gate current and device channel length.

The ultra shallow junction was formed by 2-step RTP. Phosphorus solid source(P$_{2}O_{5}$) was transfered on wafer surface during RTG(Rapid Thermal Glass Transfer) of which process condition was 80$0^{\circ}C$ and 60sec. The process temperature and time of the RTD(Rapid Thermal Diffusion) were 950~105$0^{\circ}C$ during 5~15sec respectively sheet resistances were measured as 175~320$\Omega$/m and junction depth and dopth and dopant surface concentration were measured as 0.075~0.18$\mu$m and 5${\times}10^{19}cm^{4}$ respectively. Ti-silicide was formed by 2-step RTA after 300$\AA$ Titanium was deposited. The 1st RTA (2nd RTA) was carried out at the temperature of $600^{\circ}C$(700~80$0^{\circ}C$) for 30 seconds (10~60 seconds) under N$_2$ ambient. Sheet resistances after 2nd RTA were measured as 46~63$\Omega$/D. Si/Ti component ratio was evaulated as 1.6~1.9 from Auger depth profile. Ti-Silicided n-p junction diode (pattern size : 400$\times$400$\mu$m) was fabricated under the RTD(the process was carried out at the temperature of 100$0^{\circ}C$ for 10seconds) and 2nd RTA(theprocess was carried out at the temperature of 750$^{\circ}C$ for 60 seconds). Leakage current was measured 1.8${\times}10^{7}A/mm^{2}$ at 5V reverse voltage. Whent the RTD process condition is at the temperature of 100$0^{\circ}C$ for 10seconds and the 2nd RTA process condition is at the temperature of 75$0^{\circ}C$ for 60 seconds leakage current was 29.15${\times}10^{9}A$(at 5V).

Damage induced by Si ion implantation and its annealing behavior during rapid thermal annealing were investigated by cross-sectional TEM (transmission electron microscopy) and RB ( Rutherford backscattering) spectrum. 150keV and 50keV Si ions were implanted in Si (100) at room temperature with doses of 2${\times}10^{15}cm^{-2}$. And 100keV Si ions were implanted in Si with doses from 1${\times}10^{14}cm^{-2}$. A variety of damage structures were generated by Si ion implantation such as continuous amorphous layer extending to the surface buried amorphous layer and damage clusters. Damage clusters are annealed out at the lower annealing temperature of 550 $^{\circ}C$. However, event at the temperature of 110$0^{\circ}C$ end of range loops remain in the original lower amorphous/crystal interface in the case of continuous and buried amorphous layer formation. Extended defects in the shape of zipper dislocations are also observed at the middle of the recrystallized region in the buried amorphous layer.

This paper proposes an efficient traceback method for parallel hardware implementation of the Viterbi algorithm. Compared to the conventional Viterbi algorithm where initial state for traceback is selected arbitrarily the proposed algorithm decides decoding output by analyzing the survivor paths of consecutive tracebacks. This makes Viterbi algorithm more efficient in error correction event when more than one survivor path exists. The proposed traceback algorithm together with its hardware realization is presented in this paper. Experimental results show tht the proposed algorithms is efficient in error correction in noisy channels compared to the existing algorithms.

This paper proposes a memory testable code called MTA(Memory TestAble) code which is based on error correcting code technique for testing functional faults in semiconductor memories. The characteristics of this code are analyzed and compared with those of conventional codes. The developed decoding technique for this code can reduce the decoder circuits up to 70% and obtain two-times faster decoding speed than other codes such as hamming code or Hsiao code. The MTA code is eccectively applicable to parallel testing of semiconductor memories because it has the same information length and parity length. It can detect from single error functional faults to triple error in semiconductor memories.