Multi rate circuit switching ISDN which assumes a star topology consisting of LANs(local area networks) interconnected through a backbone MAN (metropolitan area network) is considered. The stations are classified into two categories data and voice stations they are characterized by different arrival rate and session-length (holding time) statistics. We first model the data and voice terminals as finite-source stations and derive analytically exact expressions for the end-to-end blocking probabilities. For more exact evaluation, these probabilities are calculated in terms of three components:circuit blocking probability, destination busy probability and concurrent busy probability. For large size systems, we develop an develop an iterative algorithm that provides a computationally efficient and fast method for the calculation of the end-to-end blocking probabilities.

In this paper, E-plane gap-coupled rectangular microstrip antennas with parasitic elements are analyzed. The mutual coupling between the radiating edges is represented as the voltage-dependent current source. The gap coupling between the patch and parasitic element is characterized with the REC(Radiating Edges-Coupling) model, and the conventional transmission line model is used to obtain the equivalent circuit of the antenna. The return loss of the rectangular microstrip antennas with short-and open-circuit parasitic elements are calculated and compared with the measured values. The theoretical values including the mutual coupling are more in agreement with the measured values than the calculated values without the mutual coupling.

A method for suppressing unwanted resonance modes by attaching an electromagnetic wave absorber onto a metal case was studied to prevent performance deterioration of electronic devices. The electromagnetic wave absorber fabricated for this study had an attenuation characteristics above 20dB in the frequency band from 450MHz, 1150MHz. A rectangular cavity resonator whose resonance frequencies of TE$_{101}$, TE$_{102}$ modes were 900MHz, 1250MHz, respectively, was made to measure attenuation for the electromagnetic wave absorber-metal assembly. The result showed that the resonance mode for high attenuation was sensitive to the location of electromagnetic wave absorber, and the attenuation characteristics above 20dB could be obtained when electromagnetic wave absorber was properly positioned.

As a study to use Ti-silicides as interconnection material, the formation of Ti-silicides and the behavior of dopants were investigated for specimens where dopants are introduced on both single-Si substrate and poly-Si that was deposited on the single-Si. Result showed that stable C54 TiSiS12T formed above $700^{\circ}C$ and the formed TiSiS12T had bad surface roughness. And arsenics were chiefly redistributed in TiSiS12T while boron was accumulated near the interface between TiSiS11T and Si during RTA treatment.

The current-voltage characteristics at annealed Be-Cu alloy(1.8-2 wt% Be, 0.2 wt% Co+Ni) interfaces have been studied by means of the cyclic voltammetric method. The specimens were annealed in nitrogen gas($N_{2}$) furnace at 36$0^{\circ}C$ for 1.5 hours. After annealing, the vickers hardness(HV) was increased from 210 to 385. The used solutions were distilled water(H$_{2}$O), 10$^{-3}M\;CsNO_{2},10^{-2}M\;KCl,10^{-2}M\;KOH,10^{-4}M\;H_{2}SO_{4}$ aqueous electrolytes, and ethylalcohol ($C_{2}H_{5}OH$), etc. The cyclic voltammograms showed significant current-voltage characteristics between the annealed and unannealed specimens at the same conditions. The age hardening and the related surface potential barrer and dissolution effects have been observed during the whole experimental process. The dissolution process of annealed Be-Cu alloys was effectively retarded by the age hardening phenomenon. The age hardening effect also raised the surface potential barrier of Be-Cu alloys. The interfacial phenomena of Be-Cu alloys seem to be one of good models for understanding the activation process.

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.

Thin (25-103$\AA$) SiO$_2$ films are grown using the rapid thermal oxidation processing at temperatures of 105$0^{\circ}C$-115$0^{\circ}C$ for 5-30 sec, in order to investigate the characteristics of ultra thin oxide. For measuring the thickness of oxide TEM, ellipsometry, and C-V method which is taken in the condition of small surface band bending are used and compared. When neglecting the small deviation affected by both interface state and moisture charge effect, those three methods described above give similar results. In order to examine the effect of rapid thermal annealing, part of samples are annealed in N$_2$ ambient. MOS capacitors are fabricated and the characteristics of I-V and C-V are measured. Measurements show that the activation energy of initial thickness of oxide grown during the ramp-up time is of 1.125eV and the activation energy of the oxidation rate is of 0.98eV. As oxidation temperature is increased, dielectric breakdown field E$_{BD}$ is decreased due to the increase of fixed charge density N$_f$ However, E$_{BD}$ is shown to be decreased as increasing the thickness of oxide. The increase of N$_f$ in the early stage of thermal annealing results in the decrease of E$_{BD}$.

A cost model of test generation is presented in this paper. The cost of flat gate-level and hierarchical modular level test generation for combinational logic circuits are modeled. The model shows that the cost of hierarchical test generation grows as GlogGunder some assuptions, while the cost of gate-level test generation grows $G^2<$/TEX>, where G is the number of gates in a circuit under test. The cost model derived in this paper is used to explain why some test generation techniques are faster and why hierarchical test generators should be faster than flat test generators on large circuits.

This paper presents a new approach to the scheduling problem in the high level synthesis. In this approach, iterative rescheduling processes starting with ASAP(As Soon As Possible) scheduling result are performed in a branch-and-bound manner so to arrive at the scheduling result of the lowest hardware cost under the given timing constraint. At each iteration step, only the selected nodes are considered for rescheduling, and the lower bound cost estimation is performed to avoid the unnecessary attempts to search for an optimal result. This branch-and-bound method turns out to be effective in pruning the search space, and thus reducing run time considerably in many cases.