After the 1%S-Al metal is deposited, a thin oxide is formed thereon. Then, a single charged Argon(Ar$^{+}$) is ion implanted into the oxide layer, thereby causing the metal grain in the upper surface of the metal layer to become amorphous. Consequently, the grain size will be reduced and the rough surface of the metal layer flattened. However, the remainder of the metal layer beneath the upper surface thereof will still exhibit large grain size and low resistance, because the Argon ion is only implanted to characterized by a dual-sized grain structure which served to reduce interlayer stress, thereby decreasing the rate of stress migration, and to lower the resistivity of the metal line, thereby enhancing the electromigration characteristic thereof. Experiments have shown that the metal line exhibits a metal migration rate which is approximately 700% less than the control group and a standard deviation which is approximately 200% less than these group.p.

A systematic synthesis process is presented for the simulation of current-controlled grounded inductors. The process is used to obtain three circuits which are believed to be novel. One of the circuits has been implemented using linear operational transconductance amplifiers (OTA's). Computer simulation rusults are used to verify theoretical predictions. The results show close agreement between predicted behaviour and experimental performance.

MODFETs using the heterostructure of phosphorous-contained a-SiN:H: and undoped a-Si:H films have been fabricated by PECVD of SiH$_{4}$, PH$_{3}$ gases. Thecharacteristics of the devices have been invetigated and compared with conventional TFTs(CTFTs). The threshold voltage of the MODFETs was smaller than that of CTFTs, in the case of the devices using the a-SiN:H film with the relatively high phosphorous content, the threshold voltage was negative and the operation of the devices followed the depletion mode. On the other hand, on/off current ratio of the MODFETs was more than one order of magnitude higher than the CTFTs, and the field effect mobility of the former was approximately two times as high as that of the latter.

An integrated silicon pressure sensor with frequency output has been fabricated, measured, and tested. The standard bipolar process is applied and thin diaphragm was formed using EDP anisotropic etchant. Output frequency was 769 Hz-3.1 kHz at the pressure range of 0-10 psi. It operates at the temperature range of 0-50$^{\circ}C$. The frequency sensitivity was 233 Hz/psi and temperature sensitivity was 0.3 Hz/$^{\circ}C$. The power dissipation was 50mW.

InSb thin films were fabricated by zone melting recrystallization of In/Sb multilayered thin films prepared by sequential evaporation. Unreacted metal phase or dispersed metal precipitates lowered the electron mobility and the electron mobility increased with development of (111) prefered orientation. Properties of the film could be controlled by changing mzximum temperature and scanning speed, and the electron mobility as high as 12, 000 cm $^2$/Vsec could be obtained under the optimized conditions.

A recessed n-p Juction diode with the self-aligned sturcture is proposed and fabricated by using the polysilicon as an n$^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar divice and the n$^{+}$ polysilicone mitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition. As$^{+}$ dose for the doping of the polysilicon and the annealing condition using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS and the electrical characteristics are analyzed in terms of the ideality factor of diode (n), contact resistance and reverse leakage current. In addition, n$^{+}$-p junction diodes are formed by using the amorphous silicon (of combination of amorphous and polysiliocn) instead of polysilicon and their characteristics are compared with those of the standard sample. The As$^{+}$ dose for the formation of good junction is about 1~2${\times}10^{16}cm^{2}$ at given RTA conditions (1100.deg. C, 10sec).

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

In this research, we developed a new algorithm for hierarchical placement of integrated circuits. For efficient placement of a large circuit, the given circuit is recursively partitioned to form a hierarchy tree and then simulated-annealing-based placement method is applied at each level of the hierarchy to find a near optimum solution. During the placemtnt, global optimization is performed at high levels of the hierarchy and local optimization is performed at low levels. When compared with conventional placement methods, the new hierarchical placement method produced favorable results.