A new stochastic Petri nets model, called Stochastic Petri Nets Reward Model(SPNRM) is used for modeling and evaluating the performance of telecommunication protocols. We have developed a SPNRM of the TDX-10 Internal protocol, which has a packet data exchange facility between DCEs, Especially a timer and retransmission handling model is presented for error control of the data transmission phase. The stochastic Petri nets package(SPNP), a software package for SPNRM used in this paper, has been used to generate numerical results by analytical-numerical method rather than simulation. From the steady state solution of the net, it is possible to calculate automatically the performance measure of the protocol medeled with both end-to-end and link-by-link method, which are the mean response times and the throughputs.

In this paper, we evaluate the performance of a transient queueing approximation when it is applied to modeling computer communication networks. An operational computer network that uses the ISO IS-IS(Intermediate System-Intermediate System) routing protocol is modeled as a Jackson network. The primary goal of the approximation pursued in the study was to provide transient queue statistics comparable in accuracy to the results from conventional Monte Carlo simulations. A closure approximation of the M/M/1 queueing system was extended to the general Jackson network in order to obtain transient queue statistics. The performance of the approximation was compared to a discrete event simulation under nonstationary conditions. The transient results from the two simulations are compared on the basis of queue size and computer execution time. Under nonstationary conditions, the approximations for the mean and variance of the number of packets in the queue erer fairly close to the simulation values. The approximation offered substantial speed improvements over the discrete event simulation. The closure approximation provided a good alternative Monte Carlo simulation of the computer networks.

In this paper, the dual-mode burst-error-correcting decoding algorithm is adapted to the multiple trellis-coded .pi./4 shift QPSK in order to achieve the improvement of bit error rate (BER) performance over fading channels. The dual-mode adaptive decoder which combines maximum likelihood decoding with a burst detection scheme usually operates as a Viterbi decoder and switches to time diversity error recovery whenever an uncorrectable error pattern is identified. Rayleigh fading channels and Rician fading channels having the Rician parameter K=5dB are used in computer simulation, and the simulation results are compared with those of interleaving techniques. It is shown that under the constraint of the fixed overall memory quantity, the dual-mode adaptive decoding scheme gains an advantage in the BER performance with respect to interleaving strategies.

In this paper, a timer thresholds tuning algorithm is proposed, satisfying the required response time for traffic with time-critical applications and asynchronous traffic in FDDI network. Under light and medium load, priorities and timer thresholds play a minor role for medium access control. In these cases all quenes are served exhaustively with a ver high service probability and the packet loss probability approaches almost zero. Under overload condition, however, the performance of the FDDI Network is completely determined by the selection of the timer thresholds. The timer thresholds tuned by mathematical results is confirmed by simulation results using SIMAN/UNIX package. The allocation of guaranteed bandwidth can be controlled easily by tuning the timer thresholds according to the proposed rules.

The characteristics of the shielded suspended substrate coplanar waveguide(SSCPW) are analyzed by applying the point matchning method to the quasi-TEM mode approximation. The characteristic impedances and the effective dielectric constants are also calculated by changing the height of air and dielectric layer, and the strip width of SSCPW. Approaching the side strip width of SSCPW to zero, values of characteristic impedances and effective dielectric constants are agreed well with the results obtained by the variational method.

In this paper the model of the MQE-IMD-based neural trigger circuit is improved, where MQW-IMD is a new semiconductor device proposed and experimentally demonstrated by the author for the hardware implementation of the neural networks. The electron energy of AlXGa1-XAsbarrier is calculated by Ensemble Monte Carlo simulation according to the variation of Al mole fraction x and the applied electric field, whtich had been roughly estimated in the previous paper because of the difficulty to get the data. And in the consideration of the tunneling of the confined electrons within the quantum well the accuracy of the impact ionization rate is enhaned. Finally, the dependance of the frequency of pulse-train on the number of quantum wells can be calculated by modelling the effect of the distance of the induced positive charge from the cathode on the electric field at the cathode.

Three models for the transformation of ferrite chip noise filter that has jagged type of electrode into cylinderical ferrite beadfilter were presented. The properties of filters were also calculated based on the proposed models. The measured properties of ferrite chip noise filter with jagged-type electrode fabricated with Ag electrode and Ni-Zn ferrite revealed that the model 3 was the best one to describe the behavior of filters. In particular, the calculated values of model 3 agreed well with measured ones as functions of electrode patterns and chip thickness. The present study showed that the properties of fiters could be designed by theoretical models and fabricated with required characteristics.

In this paper, we propose a new technique to segment the moving target image from the natural background. This system as based on the optical BPEJTC for both detecting the moving target and automatically extracting the target image from the background by gradually eliminating the background image through the repeated correlation processes. Some computer simulation and experimental results show that the proposed system can effectively segment the moving car image from the fixed background, and that this system can be used for a fast moving target segmentation system.

Fault simulators are used for accurate evaluation of fault coverages of digital circuits. But fault simulation becomes time and memory consuming job because computation time is proportional to wquare of size of circuits. Recently, several approximate algorithms for testability analysis have been published to cope with the problems. COP is very fast but cannot be used for sequential circuits, while STAFAN can ve used for sequential circuits but requires large amount of computation because it utilizes logic simulation results. In this paper EXTASEC(An Extension of Testability Analysis for Sequential Circuits) is proposed. It is an extension of COP in the sense that it is the same as COP for combinational circuits, but it can handle sequential circuits, Xicontrollability and backward line analysis are key concept for EXTASEC. Performance of EXTASEC is proven by comparing EXTASEC with a falut simulator, STAFAN, and COP for ISCAS circuits, and the result is demonstated.

A new partitioning algorithm has been developed to implement a large circuit by using multiple field programmable gate array (FPGA) chips. While the conventional partitioning is to minimze the number of nets cut under size constraints, partitioning for multiple FPGAs has several additional constraints so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two steps whhich are the intial partitioning for global optimization and the iterative partitioning improvements for constraint satisfaction. Experismental results using the MCNC benchmark examples show that our partition method produces better results thatn those of other recent approaches on the average.

This paper introduces a general purpose Associative Processor(AP) which is very efficient for search-oriented applications. The proposed architecture consists of three main functional blocks: Content-Addressable Memory(CAM) arry, row logic, and control section. The proposed AP is a Single-Instruction, Multiple-Data(SIMD) device based on a CAM core and an array of high speed processors. As an application for the proposed hardware, we present a parallel algorithm to solve a global routing problem in the layout process utilizing the processing capabilities of a rudimentary logic and the selective matching and writing capability of CAMs, along with basic algorithms such a minimum(maximum) search, less(greater) than search and parallel arithmetic. We have focused on the simultaneous minimization of the desity of the channels and the wire length by sedking a less crowded channel with shorter wire distance. We present an efficient mapping technique of the problem into the CAM structure. Experimental results on difficult examples, on randomly generated data, and on benchmark problems from MCNC are included.