In this paper, in order to apply the idea MDPSK to TCM, we use signal set expansion and set partition by phase differences. Through this we propose the trellis-coded MDPSK. And the Viterbi decoder containing branch metrics of the squared Euclidean distance of the Lth order phase difference as well as the first order phase difference is introduced in order to improve the bit error rate(BER) in the differential detection of the trellis-coded MDPSK. The proposed Viterbi decoder is conceptually same to the sliding multiple symbol dection method which uses the branch metric with the first and Lth order phase differences. We investigate the performance of the uncoded DQPSK and the trallis-coded D8PSK in additive white Gaussian noise (AWGN) through the Monte Carlo simulation under the two cases of using and not using the Lth order phase difference metric. The study shows that trellis-coded 8DPSK is an attractive scheme for power and bandlimited systems while also improving the BER performance when the Viterbi decoder is employed to the Lth order phase order difference metric. This performance improvement has been obtained without sacrificing the bandwidth or the power efficiency.

ATM (Asynchronous Transfer Mode) has a fixed-length packet transport scheme. It is one of the promising proposals in B-ISDN.Since the packet length is fixed, it can be potentially to perform the various service to users. In this paper, a queueing model for an ATM multip`exer loaded by CBR and ON/OFF input sources is considered, and the two-queue system which each type of input sources has a queue with a finite capacity is analyzed. The cell loss probabilities for a performance measures of ATM multiplexer are derived, and are also evaluated through numerical examples. As a result, the cell loss probability of ON/OFF sources for the queue size is rapidly decreased when the multiplexed number and burstiness are increased. Since cells of the CBR source have lower priority than cells of the ON/OFF source, cell loss probabilities of CBR sources are accordingly high independently of CBR cell arrival rate when the number of CBR sources is large.

If a 4-port network is terminated by arbitrary impedances, there are great advantageges in composing systems with it. The distributed 3-dB $O^{\circ}$/180$^{\circ}$ hybrid with the impedances asymmetrically terminated is presented. In the band of UHF and VHF. on the basis of it , the new design method of small sized- hybrid using both lumped and distributed elements is also presented and analyzed At the center frequency of 900MHz. 3-dB $O^{\circ}$/180$^{\circ}$hybrid on the RT/Duroid substrate of ${\varepsilon}_{r}$=2.2, h=0.76mm is design and tested. Agreements are obtained between measured and theoretical results and at the same time the occupied area of it is reduced more than 70% compared with only distributed-type circuits.

Much time and labor has been conventionally paid for fine adjustment of circuit elements by experience to improve the characteristics of Tap-off for CATV systems. To solve the problem, in this paper, the relations between the even- and odd-mode impedance. Z$_{oe}$ and Z$_{oo}$ of symmetrical 4-port coupled-line directional coupler and power dividing characteristics of Tap-off for CATV system have been derived. After the coupling, the reflectivity and the isolation are represented by Z$_{oe}$ and Z$_{oo}$ only, the fine adjustment of all S-parameters can be performed by controling the elements of Z$_{oe}$ and Z$_{oo}$ only. Furthermore, the validity of the new fine adjustment method proposed here has been confirmed by experiments.

In this paper, an iterative inversion method in angular spectral domain is presented for microwave imaging of a perfectly conducting cylinder. Angular spectra are calculated from measured far-field scattered fields. And then both the propagating modes and the evanescent modes are defined. The center and initial shape of an unknown conductor may be obtained by the characteristics of angular spectra and the total scattering cross section (TSCS). Finally, the orignal shape is reconstructed by the modified Newton algorithm. By using well estimated initial shape the local minima can be avoided, which might appear when the nonlinear equation is solved with Newton algorithm. It is shown to be robust to noise in scattered fields via numerical examples by keeping only the propagating modes and filtering out the evanescent modes.

A microwave PIN diode 4-bit phase shifter is designed in X-band. A loaded-line type is used for the 22.5$^{\circ}$ and 45$^{\circ}$ bits, and a switched-line type for the 90$^{\circ}$and 180$^{\circ}$bits. The measured results show that the phase error and average insertion loss are less than $\pm$5.4$^{\circ}$and 7.2dB, respectively, over a 9.75~10.25GHz frequency band.

The resonator using the shielded coplanar waveguide [S.C.P.W.] bounded by the rectangular waveguide is designed. The resonant frequency is obtained by using the full-wave analysis method. The fringing capacitances of the open-ended center strip in the resonator are obtained from the equivalent circuits by 3 different methods.

For distortion-invariant recognition of Korean characters, a holographic implementation of an optical associative memory system is proposed. The structure of the proposed system is a single-layer neural network employing interconneclion matrix, thresholding and feedback. To provide the interconnection matrix, we use two CGII's which are placed on intermcdiate plane of cascaded Vander Lugt corrclators to form an optical memory loop. The holographic correlator stores reference images in a hologram and retrives them in a coherently illuminated feedback loop. An input image which maybe noisy or incomplete, is applicd to the system and simultaneously correlated optically with all of the stord images. These correlations are throsholed and fed back to the input, where the strongest correlation reinforces the input image. The enhanced image passes arround the loop repeatedly, approaching the stored image more closely on each pass until the system stabilizes on the desired image. The computer simulation results show that the proposed Korean Character recognition algorithm has high discrimination capability and noise immunity.

A low noise erbium doped fiber amplifier for optical preamplification has been demonstrated. The amplifier incoporates an optical isolator in its midway to prevent decrease of population inversion at the input port due to backward traveling amplified spontaneous emission. Then, high gain and low noise can be achieved simultaneously. A small signal gain of 34dB and a noise figure of 5.5dB have been achieved. With this amplifier, we obtained a receiver sensitivity of -39.7dBm with back to back configuration and -39.3dBm with 47km normal fiber for 10$^{-9}$BER at 2.5Gbps direct modulated optical signal.

In this paper, a binary phase extraction joiont transform correlator (BPEJTC)system is proposed as a new phase-type optical correlator in which the correlation errors and DC component are dramtically reduced and optical efficiency and correlation performance are also improved by reconstructing the joint transform power spectrum (JTPS) of the conventional joint transform correlator (JTC)system form which the autocorrelation and crosscorrelation siganls generated in each self-plane are removed, and the binary phase function is extracted from the phase value of the reconstructed JTPS. Through some computer simulation and optical experimental results, the possibility of the implementation of the real-time multi-target tracking and recognition system is also suggested.

We describe the design, fabrication, and performance of the optical fiber-photodiode 1$\times$12 arry module using mesa-type InS10.53T GaS10.47TAS/INP 1$\times$12 PIN photodiode array. We fabricated the PIN PD array for high-speed optical fiber parallel data link optimizing quantum efficiency, operating speed sensitivity from the PIN-FET structure, and electrical AC crosstalk. For each element of the array, the diameter of the photodetective area is 80 $\mu$m, the diameter of the p-metal pad is 90 $\mu$m, and the photodiode seperation is 250 $\mu$m to use Si v-groove. Ground conductor line is placed around diodes and p-metal pads are formed in zigzag to reduce Ac capacitance coupling between array elements. The dark current (IS1dT) is I nA and the capacitance(CS1pDT) is 0.9 pF at -5 V. No signifcant variations of IS1dT and CPD from element to element in the array were observed. We calulated the coupling efficiency for 10/125 SMF and 50/125 GI MMF, and measured the responsivity of the PD array at the wavelength is 1.55 $\mu$ m. Responsivities are 0.93 A/W for SMF and 0.96 A/W for MMF. The optical fiber-PD array module is useful in numerous high speed digital and analog photonic system applications.

To realize high accuracy and high speed we developed a new self compensation scheme and applied it to a 10-bit D/A converter. This circuit can compensate the device mismatch without interrupting the D/A converter operation. With the compensation circuit,INA decreased down to 0.22LSB from 0.47LSB. The device was fabricated using a 0.8$\mu$m CMOS process. The area of the D/A converter core is 3.2mm$^{2}$ and the area of the compensation part is 0.64mm$^{2}$.

In this paper, The electrical properties of MOS capacitors and transistoras with gate of in-situ doped amorphous Si and poly Si doped by POCI$_3$. Under constant current F-N stress, MOS capacitors with in-situ doped amorphous Si gate have shown the best resistance to degradation in reliabilty properties such as increase of leakage current, shift of gate voltage (V$_{g}$). shift of flat band voltage (V$_{fb}$) and charge to breakdown(Q$_{bd}$). Also, MOSFETs with in-situ doped amorphous Si gate have shown to have less degradation in transistor properties such as threshold voltage, transconductance and drain current. These improvements observed in MOS devices with in-situ doped amorphous Si gate is attributed to less local thinning spots at the gate/SiO$_2$ interface, caused by the large grain size and the smoothness of the surface at the gate/SiO$_2$ interface.

In this paper, electrical and reliability properties of N$_2$O oxides, grown at the temperature of 95$0^{\circ}C$ and 100$0^{\circ}C$ to 74$\AA$, and 82$\AA$. respectively, using NS12TO gas in a conventional furnace, have been compared with those of pure oxide grown at the temperature of 850 to 84$\AA$ using O$_2$ gas. Initial IS1gT-VS1gT characteristics of N$_2$O oxides were similar to those of pure oxide, and reliability properties of N$_2$O oxides, such as charge trapping, interface state density and leakage current at low electric field under F-N stress, were improved much better than those of pure oxide. But, with increasing capacitor area. TDDB characteristics of N$_2$O oxides were more degraded than those of pure oxide and this degradation of TDDB characteristics was more severe in 100$0^{\circ}C$ N$_2$Ooxide than in 95$0^{\circ}C$ N$_2$O oxide. The improvement of reliability properties excluding TDDB in N$_2$Ooxides was attributed to the hardness of the interface improved by nitrogen pile-up at the interface of Si/SiO$_2$, but on the other hand, the degradation of TDDB characteristics in N$_2$O oxides was obsered due to the increase of local thinning spots caused by excessive nitrogen at interface during the growth of N$_2$O oxides.

This paper proposes a new TTL-to-CMOS converter which has low power dissipation. This converter has no static power dissipation for typical TTL output voltage levels. The simulatio result shows that the power dissipation is reduced to about 1/20 of conventional level converter using CMOS inverters. It also has hysteresis due to the positive feedback which makes the converter noise immune. The logic threshold voltages in the hysteresis characteristic can be optimized by changing the size ratios of the transistors.

A kink due to the lasing of the first transverse mode in laser diodes is investigated using rate equations based on the spatial hole burning model. An analytic expression for the kink power is derived and the result agrees well with experimental results. It is also shown that the position of a kink can be identified in the electrical derivative characteristics as well as in light output vs, current characteristics.

In order to study the effect of D.C resistivity of sample on electromagnetic loss of ferrite at microwave frequency, samples were prepared for having differences in resistivity of an order of two. Microwave permeability($\mu$), permitivity($\varepsilon$) and effective linewidth(${\Delta}H_{eff}$), and ferromagnetic resonance linewidth(${\Delta}$H) were characterized. Tan${\delta}{\mu}$, tan${\delta}{\varepsilon}$ and ${\Delta}H_{eff}$ were decreased with increasing the resistivity and (${\Delta}$H) was increased with increasing Fe concentration, which was due to an increase of anisotropy magnetic field (=Ha).

Through high level synthesis, designers can obtain the precious information on the area and speed trade-offs as well as synthesized datapaths from behavioral design descriptions. While previous researches were concentrated on the synthesis of pipelined, datapaths with fixed DII (Data Initiation Interval) by inserting delay elements where needed, we propose a novel methodology of synthesizing pipeline structures with variable DIIs. Determining the time-overlapping of pipeline stages with variable DIIs, the proosed algorithm performs scheduling and module allocation using the time-overlapping information. Experimental results show that significant improvement can be achieved both in speed and in area.

Stochastic computation is adopted to reduce the silicon area of the multipliers in implementing neural network in VLSI. In addition to this advantage, the stochastic computation has inherent random errors which is required for implementing Boltzmann machine. This random noise is useful for the simulated annealing which is employed to achieve the global minimum for the Boltzmann Machine. In this paper, we propose a method to implement the Boltzmann machine with stochastic computation and discuss the addition problem in stochastic computation and its simulated annealing in detail. According to this analysis Boltzmann machine using stochastic computation is suitable for the pattern recognition/completion problems. We have verified these results through the simulations for XOR, full adder and digit recognition problems, which are typical of the pattern recognition/completion problems.

본 논문에서는 조합회로에 있어서 고장 시뮬레이션의 고속화를 위한 효율적인 병렬 평가 알고리듬을 제안한다. 제안한 알고리듬은 고장소자의 평가 및 전파에 있어서 병렬법, 연역법 그리고 동시법의 장점을 이용하고 있기 때문에 시뮬레이션의 고속화를 실현할 수 있을 뿐만 아니라 다치(multi-valued) 신호를 쉽게 취급할 수 있다. 또한, 동일한 신호선에서 발생하는 액티브(active)고장을 동일한 고장 그룹으로 할당하므로써 병렬연산의 효율을 증가시키기 위한 고장의 그룹화(fault grouping) 방법을 제안한다. 제안한 알고리듬은 C언어로 구현하였으며, ISCAS '85 Benchmark 회로에 대한 실험 결과 종래의 동시법과 비교하여 약 2.6배에서 8.2배 정도의 고속화가 실현되었다.

In the design of modern computer systems, the speed gap between the CPUs and DRAMs has been a major concern. To relieve this problem at a low cost, several new DRAM architectures have been proposed. This study is aimed at evaluating quantitatively the impact of the new DRAM architectures (synchronous DRAM. dual-RAS synchronous DRAM, and enhanced DRAM) on the memory system performance. We developed a cache and memory simulator and performed various experiments using the traces generated from four benchmark programs. The simulation results show that the new DRAM architectures offer a better performance than a conventional one by 5~30% in a low cost system and their improvement in a high performance system is less than 1%. However, for resonable multiprogramming workoads, additional performance improvement of about 10~28% is expected in a high performance system while 1~3% in a low cost system.

The distributed arithmetic approach has been commonly recognized as an efficient method to implement the inner-product type of computation with fixed coefficients such as DCT/IDCT. This paper presents a novel architecture and the implementation of 2-D DCT/IDCT VLSI chip based on distributed arithmetic. The main feature of the proposed architecture is a fully 2-bit serial pipeline and parallel structure with memory-based signal processing circuitry, which is efficient to the implementation of the bit-serial operation of distributed arithmetic. All modules of the proposed architecture are designed with NP-dynamic circuitry to reduce the power consumption and to increase the performance. This chip is applicable in HDTV systems working at video sampling rate up to 75 MHz.

This paper proposes a delay fault test technique for ICs and PCBs with the boundary-scan architectures supporting ANSI/IEEE Std 1149.1-1990. The hybrid delay fault model, which comprises both of gate delay faults and path delay faults, is selected. We developed a procedure for testing delay faults in the circuits with typical boundary scan cells supporting the standard. Analyzing it,we concluded that it is impractical because the test clock must be 2.5 times faster than the system clock with the cell architect-ures following up the state transition of the TAP controller and test instruction set. We modified the boundary-scan cell and developed test instructions and the test procedure. The modified cell and the procedure need test clock two times slower than the system clock and support the ANSI/IEEE standard perfectly. A 4-bit ALU is selected for the circuits under test. and delay tests are simulated by the SILOS simulator. The simulation results ascertain the accurate operation and effectiveeness of the modified mechanism.

Timers are commonly used in hardware design for time delays that are to be much longer than the system clock period. In this paper, we present a method by which we can synthesie a hardware containing timers that implement long time delays described in VHDL. Because, in general, timers require high hardware cost, they must be utilized as efficiently as possible. To solve this problem we define a graph model and propose an algorithm that uses the graph model to minimize number of timers. A preliminary experimental result show that the algorithm implements all required time delays using minimum number of timers.