in this paper, we analyzed CDD-DLL code tracking loop for tracking of direct-sequence spread-spectrum signals in a multipath fading channel. The multipath fading channel is modeled as two-ray rayleigh fading channel which is well applicable in a land mobile communication environments. We use trackin jitter variance and mean-time-to-lose-lick as performance measures. From the numerical resutls, it is shown that the effect of multipath fading decreases as SNR/bit increases. Also it is shown that CDD-DLL provides superior jitter performance compared with noncoherent DLL and jitter performance improvement is more significant for a two-ray rayleigh fading channel than an AWGN channel.

The performance of tau-dither loop (TDL) is evaluated for a direct-sequence spread-spectrum system in a multipath fading channel. The multipath fading channel is modeled as a two-ray rayleight fading channel. The code tracking perfomrance of TDL is analyzed in terms of tracking jitter and mean-tiem-to-lose-lick (MTLL). The tracking jitter performance is degraded while MTLL perfomrance is improved with increasing discriminator offset and decreasing power ratio of main to second paths. It is shown that for a large bit SNR, the effect of multipath fading becomes more significant. And it is also shown that tracking jitter and MTLL performance is less sensitive to delay spacing and discriminator offset for a small bit SNR than for a large bit SNR.

By integrating WDM to OPS unit which plays an improtant role for the reliability of CPN, we made it possible to provide CATV, VOD, and high-speed data services simultaneously and to meet easily the requirements for new services in the future. For the design of optimal system, the link analysis of power budget has been perfomred. Also, the prototyped system has been tested with STM-1 level signals to confirm functions such as transmission, distribution, and protection. The results proved that when occurred out-of-order or recovery of ONU, the system did the pertinent switching with minimum loss for high-speed data services. Also for video distribution services, the system has distributed STM-1 level signals sucessfully.

Syntax notation one (ASN.1) defined by ITU-T and ISO, is a formal abstrct specification language which has been widely used in international standards specifiation to inteconnect distributed open systems. It si necessary to have well defined encoder/decoder modules which taranslate ASN.1 datum to BER octets stream to interconnect distributed open systems. In this paper, we designed and implemented a new ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which atutomatically translates and ASN.1-to-C compiler, called HYASNC (hanyang ASN.1-to-C), which automatically translates an ASN.1 specification into C-language BER encoders and decoders with simple and neat I/F for the defined ASN.1 data types, and enhanced BER (basic encoding rules)encoding/decoding libraries, called HY(hanyang)BER library, and useful utility functions. And this paper discusses HYASNC compiler, HY BER runtime library's design and implementation principles, and also evaluates the perfomrance of HY BER library and the interoperability with other ASN.1 compilers.

The purpose of this study is to develop the miniaturized duplexer filter for mobile communications using high dielectric constant (${\varepsilon}$r > 100, 180) ceramic resonators. Duplexer filter was ocmposed of ceramic resonators which has been developed using BNT system and SCT system, respectively. Developed duplexer filter was formed to have Tx frequency band at 836.5 (($\pm$12.5)MHz and Rx frequency band at 881.5 ($\pm$12.5)MHz. Insertion loss at Tx frequency band was 1.41dB and 1.46dB, insertion loss at Rx frequency band was 3.49dB and 3.65dB, respectively. Especially, duplexer filters using dielectric cermaics with ${\varepsilon}$r = 180 were 8% smaller than commercially manufactured duplexer filters using dielectric ceramics with ${\varepsilon}$r = 90 by murata.

In this paper we propose a new timing recovery method by means of utilizing service data filling rate instead of timing information of transmitter. A proposed algorithm controls the phase locked loop in the opposite direction ot data filling rate of FIFO in receiver, and it is based on the fact that average of cell jitters is zero. The proposed method is simple compared with timing information method of transmitter. It can be utilized for timing recovery in synchronous digital hierarchy as well as in plesiochronous digial hierarchy without common reference clocks in end-to-end erminals. We implement the interactive video communication system and test the proposed algorithm. As a result, we hav econfirmed that it yields good perfomrnces in terms of jitters characteristics and hardware complexity.

In this paper, we analyze packaging data of th eprinted board assemblies (PBAs) of an ATM switching system (the first network test bed) by statistical methods and discuss the relation between devices packaging area of a PBA and power consumption by a regression nalysis method. As a result, we evaluate the maximum power consumption of the PBA. And, this paper presents a forecasting mehtod of the packagable maximum power consumption per a PBA when TTL devices are replaced by ASIC or FPGA ones in a PBA. And, we forecast the possibility of packaging ATM switch circuit packs in the near future form a statistical viewpoint. These evaluation and forecasting results can reduce much development cost and time because trial nd error will not be made using these useful data when phase II ATM switching system will be realized in the near future.

In this study forty-five X-bnd rectangular microstrip patch antennas fed by microstrip line using ${\lambda}$/4 transformer were fabricated on teflon substrates with low high permittivities and varous thickness (substrate thickness : 0.6 ~ 2.4 mm, permittivities : 2.15 ~ 10.0), and effects of permittivity and electrical thickness on antenna characteristics were studied with measured return loss (1/S$_{11}$) and resonant frequencies. When substrate electrical thickness was greater than 0.060 ${\lambda}_{0}$return loss was very good and genrally more than 20 dB, but resonance characteristics was somewhat unstable. The more than 0.088 ${\lambda}_{0}$ the thickness was, the more unstable it was. As a result, in the rest range except 12, 13 GHz we had very good mesured return loss iwth greater than 20 dB, and in the range 7 to 9 GHz resonant frequencies were within $\pm$2 % error, on ${\epsilon}_{r}$=5.0, height = 2.4 mm substrate.

A simpel formular is proposed for the analysis of gate delay of CMOS gate in the low V$_{GS}-V_{TH}$ scaling. The effects of magnitude of V$_{GS}-V_{TH}$ on gate delay can be readily found through the formula so that it can be used ot design the device parameters in the low V$_{DD}$ CMOS circuits. The measured sresutls confirm the usability of the proposed formula and quantifies the improtance of V$_{TH}$ effects on gate delay under low voltae operation. Applying the formula to the prototype NMOSFET devices representing the five generations of technology, the impacts of the V$_{GS}-V_{TH}$ on the various aspects of the circuit and device characteristics are investigated in a consistent manner.

In this ppaer, temeprature dependent transport and heat transport models have been incorperated to the two dimensional device simulator SNU-2D provides a solid bse for nonisothermal device simulation. As an example to study the nonisothermal problem. we consider SOI MOSFET's I-V characteristics have been simulated and compared with the measurements. It is shown that negative slopes in the Ids-Vds characteristics are casused by the temperature dependence of the saturation velocity and the degradation of the temperature dependence mobility. Also it is shown that the kink effect occurs when impact ionization near the drain produces a buildup of holes in this isolated device island, and the hysteresis is caused by the creation of holes in the channel and their flow to the source.

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.

Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scalling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakge is majorly due to the capacitive coupling between the floating gates of the unselectd cells and the bit line of selected cell. In this paper, a new programming method to redcue significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the soruce during programming unlike the conventional programming method in which the source is grounded. The resutls of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35.mu.m effective channel length and 1.0.mu.m effective channel width show that the subthreshold leakage in the unselectd cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased ot a little positive voltage during programming. On the other hadn, the positive bias on the source is found to have little effects on the programming speed of the EPROM.

The variation of the interfacial and the electrical properties of SiO$_{2}$TiW layers as a function of anneal temperature was extensively investigated. During the deposition of SiO$_{2}$ on TiW chemical bonds such as SiO$_{2}$, TiW, WO$_{3}$, WO$_{2}$ TiO$_{2}$ Ti$_{2}$O$_{5}$ has been created at the SiO$_{2}$/TiW interface. At the anneal temperature of 300$^{\circ}C$, WO$_{3}$ and TiO$_{2}$ bonds started to break due to the reduction phenomena of W and Ti and simultaneously the metallic W and Ti bonds started to create. Above 500$^{\circ}C$, a part of Si-O bonds was broken and consequently Ti/W silicide was formed. Form the current-voltage characteristics of Al/Sico$_{2}$(220$\AA$)/TiW antifuse structure, it was found that the breakdown voltage of antifuse device wzas decreased with increasing annealing temperature for SiO$_{2}$(220$\AA$)/TiW layer. When r, the insulating property of antifuse device of the deterioration of intermetallic SiO$_{2}$ film, caused by the influw of Ti and W.W.

Tungsten silicide films were deposited on the phosphorus-doped poly-Si/SiO$_{2}$/Si-substrates by LPCVD (low pressue chemical vapor deposition). The formation and various properties of tungsten silicide processed by furnace annealing in N$_{2}$ ambient were evaluated by using XRD. AFM, 4-point probe and SEM. And the redistribution of phosphorus atoms has been observed by SIMS. The crystal structure of the as-deposited tungsten silicide films were transformed from the hexagonal to the tetragonal structure upon annealing at 550.deg. C. The surface roughness of tungsten polycide films were found to very smoothly upon annelaing at 850.deg. C and low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide low phosphorus concentration in polysilicon layer. The sheet resistance of tungsten polycide films are measured to be 2.4 .ohm./ㅁafter furnace annealing at 1100.deg. C, 30min. It was found that the sheet resistance of tungsten polycide films upon annealing above 1050.deg. C were independant on the phosphorus concentration of polysilicon layer and furnace annealing times. An out-diffusion of phosphorus impurity through tungsten silicide film after annealing in $O_{2}$ ambient revealed a remarkably low content of dopant by oxide capping.

It is difficult to fabricate precise resistors for the analog integrated circuits using MOS technology. Until now polysilicon resistors were used at the analog integrated circuits, but some deviations of resistance and sensitive variation processes still cause their misactions. In order to improve these misactions, we suggest a CMOS resistor cell which provides precise resistance and excellant linearity. Also we designed the second order active low pass filter using the CMOS resistor cells and verified their superior performances compared to the actual resistors.

In this paper, we analyze the variations of thermal characteristics of LD (laser diode) arrays packaged by a flip-chip bonding method. When we simulate the temperature distribution in LD arrays with a BEM (boundary element method) program coded in this paper, we find that thermal crosstalks in LD arrays packaged by the flip-chip bonding method increases by 250-340% compared to that in LD arrays packaged by previous methods. In the LD array module packaged by the flip-chip bonding technique without TEC (thermo-electric cooler), the important parameter is the absolute temperature of the active layer increased due cooler), the important parameter is the absolute temperature of th eactiv elayers of LD arrays to thermal crosstalk. And we find that the temperature of the active layers of LD arrays increases up to 125$^{\circ}C$ whenall four LDs, without a carefully designed heatsink, are turned on, assuming the power consumption of 100mW from each LD. In order to reduce thermal crosstalk we propose a heatsink sturcture which can decrease the temeprature at the active layer by 40%.

Diffraction gratings were designed to generate multiple beams for the real-time optical interconnection in free-space using a liquid crsytal television. Multi-level phase gratings consisted of stepped phase value, 0 to 2$\pi$, and generate a 5$\times$5 spot array, and V-shaped spot patterns which have a maximum diffraction efficiency of 78.84%. Simulated annealing technique was used to determine phase states of each pixel having uniform intensity and high diffraction efficiency. Through the optical interconnection experiments, we compared the diffraction characteristics of beam paterns obtained by binary-level, four-level, and eight-level phase gratings.

This paper invetigates estimation methods of mapping parameters in object-oriented coding. In this paper, we propose a fast parameter estimation method with its performance similar to that of the conventional methods. We employ hierarchical structure in difference images to redcue the computational complexity and also combine conventional six- and eight-mapping parameter estimation methods to compensate for the performance degradation caused by employment of hierarchical structure. Computer simulation shows that the proposed mehtod gives results similar to conventional methods with greatly reduced computational complexity.

As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

This paper proposes two new dynamic CMOS logic styles, called ZMODL (zipper-MODL) and EZMODL (enhanced-ZMODL), which can reduce more area dnd propagation delya than conventional MODL (multiple output domino logic). The 32-bit CLAs(carry look-ahead adder) are designed by ZMODL, EZMODL circuits, and their operations are verified by SPICE 3 with 2$\mu$ double metal CMOS parameters. The results shwo that the CLA designed by EZMODL circuit has achived 32-bit additin time of less than 4.8NS with VDD=5.0V and 8% of transistors cn be redcued, compared to the CLA designed by MODL. The EZMODL logic style can improve the performance in the high-speed computing circuits depending on the degree of recurrence.