Degradation of communication quality is due to transmission error rather than quantization noise when DPCM signal is transmitted over a heavily noise channel. The communication quality can be improved by employing an error correcting code to the DPCM signal transmission over such a channel. We considered both quantization noise and transmission error simultaneously in evaluating the signal to noise ratio. To efficiently improve the signal to noise ratio, we analyze the unequal symbol error probability of convolutional code, and encoded to more protect significant symbols from channel errors than least ones, so that the signal to noise ratio is improved. We derived related formulas and also made computer simulations.

A new algorithm for calculation of overcurrent and overvoltage at load for parallel two-wire transmission line with nonlinear protection circuits induced by and external electromagnetic pulse is suggested. The rigorous solution is obtained for a particular type of the incident waveform and protection circuit. The validity of our algorithm is checked by comparing numerical results to the analytic solution in the particular case.

New design method of small-sized 3-dB $0^{\circ}/180^{\circ}$ ring hybrid and Wilkinson power divider using both lumped elements and distributed elements are presented. At the center frequency of 900 MHz 3-dB $0^{\circ}/180^{\circ}$ ring hybrid and Wikinson power divider are designed and tested. Good agreements are obtained between measured and theoretical modeling results, and at the same time the circuit area is reduced by more than 70% compared with the discributed-type circuits.

In order to improve the radiation characteristics of the microstrip antenna, microstrip array antenna consisting of one center patch fed by a coaxial probe and several patches directly coupled to the E-plane by microstrip line is analyzed. The equivalent circuit of the array antenna is represented by the conventional transmission line and the various parameters, such as the mdicrostrip line length, the patch length and the feed point location are calculated to improve the radiation pattern for 5-patch array antenna which has the equal patch width. The 5-patch array antenna with the radiation pattern which has low sidelobe level and narrow beam width is fabricated and then the measured results are compared with the computed values and the results of the single patch microstrip antenna too.

The influence of physical parameters (Al mole fraction, thickness, doping concentration) in the window and emitter on the efficiency characteristics of heteroface p-$Al_{x}Ga_{1-x}As/p-GaAs/n-GaAs/n^{+}$-GaAs solar cell is investigated. The maximum efficiency theoretically calculated in this device is obtained when a thickness of the window is in a range of (400-1000))$\AA$and a thickness/doping concentration of the emitter is in a range of (0.5-0.8)$\mu$m/(1-7)${\times}10^{17}cm^{-3}$, respectively. Also is the efficiency improved according to the increase of Al mole fraction in the indirect gap window(0.41${\le}x{\le}1.0$). The optimum designed heteroface cell with an area of 0.165cm$^2$fabricated using MOCVD exhibits an active area conversion efficiency of 17%, having a short circuit current density of 21.2mA/cm\ulcorner an open circuit voltage of 0.94V, and a fill factor of 0.75 under ELH-100mW/cm$^2$illumination.

It is well known that the conventional differential source-coupled pair uses gates as its input terminals. This input pair provids a high open-loop gain, a large CMRR, and a good PSRR. For these reasons, the input pair has been used widely as an input stages of the differential amplifiers, but a narrow linear input range of this structurelimits its application in the area of some analog circuit design. A novel CMOS source-coupled backgate pair is proposed in this paper. The bulk of MOSFET is exploited and input devices are biased to operate in ohmic region. With this topology, the backgate pair of the wide linear input range and variable transconductance can be obtained. This backgate input differential stage is realized with the size of W/L=50/25 MOSFETs. The results show the nonlinear error is less than $\gamma$1% over 10V full-scale range for the bias current of 200$\mu$A with 10V single power-supply.

The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.

An effective and accurate delay time model is the key problem in the simulation and timing verification of CMOS logic circuits. We propose a semi-analytic CMOW delay time model taking into account the configuration ratio, the input waveform slope and the load capacitance. This model is based on the Schichman Hodges's DC equations and derived on the optimally weighted switching peak current. The parameters necessary for the model calculation are automatically determined from the program. The proposed model is computationally effective and the error is typically within 10% of the SPICEA results. Compared to the table RC model, the accuracy is inproved over two times in average.

This paper presents an efficient algorithm for incremental and hierarchical design rule checking of VLSI layouts, and describes the implementation of a layout editor using the proposed algorithm. Tracing the sliced edges divided by the intersection of the edges either ina polygon or in two polygons (Sliced-Edge Trace), the algorithm performs VLSI pattern operations like resizing and other Boolean operations. The algorithm is not only fast enough to check the layouts of full-custom designs in real-time, but is general enough to be used for arbitrarily shaped polygons. The proposed algorithm was employed in developingt a layout editor on engineering workstations running UNIX. The editor has been successfully used for checking, generating and resizing of VLSI layouts.

This paper presents an algorithm for technology-dependent logic optimization and technology mapping, and describes a performance-driven logic synthesis system, SILOS, implemented based on the proposed algorithm. The system analyzes circuits and resynthesizes the critical sections such that generated circuit operates opertes within time constraints, using only gate types supported by library for direct implementation. Experimental results show that the system can be a viable tool in synthesizing high-performance logic circuits.

MoSi$_2$ was formed by RTA (Rapid Thermal Annealing at 600-1200$^{\circ}C$) under Ar ambient from the Mo-Si mixture film which was deposited on single and poly-Si substrates. The MoSi$_2$ film was investigated by SEM, X-ray diffractometer, four-points probe and AES profile. It was found that the resistivity, the surface roughness, and the formation temperature of MoSi$_2$ were independent on the type of Si substrates. The formation of MoSi$_2$ started from 800$^{\circ}C$ and the phse transformation was completed at 1000$^{\circ}C$. The stable MoSi$_2$ with the resistivity of 74${\mu}{\Omega}$-cm was formed at 1200$^{\circ}C$.