In DQDB networks, the bandwidth can be increased considerably be using the EN(Erasure Node) algorithms and DR(Destination Release) algorithms. However, the important issue in implementing them is using method of extra capacity fairly. To improve it, this paper proposes AEN(Adaptive Erasure Node) algorithm which erasure function is activated by network traffic load. Its functional architecture consists of SESM, RCSM, LMSM in addition to the basic DQDB state machines (DQSM, RQM). The SESM and RCSM state machines are placed in front of the DQSM and RQM state machines in order for the node to take advantage of the newly cleared slots. This paper also presents some simulation results showing the effect of AEN algorithm on access delay, throughput and segment erasing ratio in the single and multiple priority networks. The results show that the AEN algorithm offer the better performance characteristics than existing algorithms under overload conditions.

The national standards of microwave power in X-band and Ku-band were established using the waveguide microcalorimeters and have been disseminated to the related industries to contribute to industrial development. Through the comparisons and analysis of the measured effective efficiencies for waveguide thermistor mounts in the recent years, the accuracy for maintenance of power standards was confirmed.

We have investigated microwave dielectric properties of TiO$_{2}$ added (Pb$_{1-x}$Ca$_{x}$)ZrO$_{3}$ Ceramics with x=0.33, 0.35, and 0.37 sintered at 1400$^{\circ}C$ for 2 h. For additions of up to 3wt% of TiO$_{2}$ in (Pb$_{0.63}$ Ca$_{0.37}$)ZrO$_{3}$ (x=0.37), TiO$_{2}$ was completely soluble in (Pb, Ca)ZrO3 phase and did not affect the grain size of ceramics. Dielectric constant and temperature coefficient of resonant frequency increased due to the formation of solid solution, whereas Q value decreased linearly as TiO$_{2}$ increased up to 1 wt%. However, the dielectric loss was very high as TiO$_{2}$ exceeded 2 wt%. It was also shown that as Ca ion content in 0.5 wt% TiO$_{2}$ added (Pb$_{1-x}$,Ca$_{x}$)ZrO$_{3}$ decreased from x=0.37 to x=0.33, dielectric constant increased and Q value decreased.

In this paper, a simple design method is represented for a contiguous-band waveguide manifold diplexer which employs a half-wavelength line at the input port of the singly terminated bandpass filterand has resonant-slot coupled E-plane T-junctions. This design method is based on the fact that the input impedance characteristics of the singly terminated bandpass filter are approximately unchanged when a resonant slot and a half-wavelength line at the input port of the filter are employed. This design method is also applicable to the design of the multiplexer. A contiguous-band waveguide manifold diplexer using the post coupled cavity filters is designed, constructed, and tested. The computed and experimental results show the validity of the theory.

An erbium doped fiber amplifier(EDFA) pumped by aingle 1.48$\mu$m LD was fabricated, and its gain and noise characteristics were measured. As a signal source, 1548 nm wavelength DFB LD was used. The small signal net gain of the EDFA module was 21.8 dB with maximum gain coefficient 0.7dB/mW for the erbium fiber length of 17.6 m, the pump power of 58 mW, and an input signal power of -25 dBm, respectively. The saturation power of the EDFA was 1 dBm for the input signal power of -5 dBm and the noise figure, measured by using an optical spectrum analyzer, was 5.8 dB for the input signal power of -40 dBm.

This paper describes the implementation of a layout generation system for the gate matrix style to implement multi-level logic. To achieve improved layouts from general net lists, the proposed system performs flexible net binding for series nets. Also the system reassings gates by the heuristic information that shorter net lengths are better for the track minimization. By track minimizing with subdividing layout column information, the system decreases the number of necessary layout tracks. Experimental results show that the system generates more area-reduced (approximately 7.46%) layouts than those by previous gate matrix generation systems using net list inputs.