In this paper, we propose an efficient computational algorithm that can reduce significantly the computational complexity of the ML optimum multiuser detector known as the most excellent detector in synchronous code division multiple access channels. The proposed detector uses the sequential detection algorithm based on the alternating maximization appraoch to obtain the ML estimates. As initial estimates for this sequential algorithm, we can use the estimated values obtained by the conventional single-user detector, the linear decorrelating multiuser detector, or the decorrelating decision-feedback muliuser detector, the linear decorrelating multiuser detector, or the decorrelating decision-feedback multiuser detector. We have performed computer simulations in order to see the convergence behaviors and the detection performance of the propsoed algorithm in terms of initial algorithms and the number of users, and then to compare the computational complexity with that of the ML optimum multiuser detector. From the results, we have seen that the proposed alternating maximization detector has nearly equal detction performance with that of the ML optimum multiuser detctor in only a few iteration.

In this paper, the reverse link performance evaluation with synchronous CDMA is analyzed in the PCS system, which is the schem based on proposed method of KMT-PCS to increase the capacitance of cellular CDMA system. We make the baseband system model of CDMA reverse link, and then analyze system performance and subsystem techniques considering effect of channel and power control that are improtant factor influencing system performance in the PCS system. Based on this result, the paper presents primary technique analyses required at synchronous reverse link proposed by the KMT, which compose of initial synchronization range in initial synchronization step and control signal period in the synchronization maintenance step.

In this paper, we propose a fast code acquisition method that can reduce drastically the mean acquisition time of the direct sequence spread spectrum (DS-SS) system by using and integrated search and verification (ISV) scheme. The proposed method performs simultaneously the search and verification processes at every search cell, through storing sufficiently long signal samples enough to perform the verification process form the previously received samples. We analyze and acquisition performance in the case of Gaussian channel to evaluate theacquisition perfomrance of the proposed method. From the simple numericl analysis result, we have shown that the acquisition performance of the proposed method is better than that of the conventional serial search method, and the performance improvement becomes more prominent as the channel environment becomes degraded.

In this paper, we analyze the delay characteristics of the multimdedia traffic in B-ISDN, and propose a weighted variable-size window estimator considering the QoS characteristics of the media and the variable delay characteristics of the networks, and present a delay estimator-based synchronization protocol for the efficient synchronization in ATM-based B-ISDN. The proposed estimator assigns a high weight value to recent cells arrived in the receiver, and suitably adjusts window size in order to efficiently adapt to delay variation by the prameter to detect the delay variation of the networks. The proposed synchronization protocol estimates end-to-end delay by the weighted variable-size window estimator, and dynamically schedules th evirtual channel of the transmitter to playout multimedia data on time in the receiver. Also, we evaluate the performance of the delay estimator, which is the most importnat functional element in our proposed synchronization protocol, by the simulation and analyze the results of the simulation.

Various types of B-ISDN bearer connection can take place according to access types of endpoint equipments in call and number of connectio between endpoints. In this paper, performance of application signalling protocol on three basic facilities of B-ISDN CS-2 signalling system, such as connection of point-to-point, point-to-multipoint and multiconnection call, is evaluated and compared. For performacne evaluation, experimental model of B-ISDN application signalling protocol is implemented and respective message processing time of each process is measured. By applying message processing time to local exchange system, cal processing capacity of application signalling protocol on three basic connection types is evaluated by simulation method. In this paper, local exchange system is considered to have two ATM NNI links and four ATM UNI links.

This paper presents performance evaluation of a new high speed inter-processor communication(HIPC) network for large capacity and high performance digitral switching system. The HIPC structure implements the fast reservation and concurrent arbitration technique (modified round-robin arbitration). The performance evaluation of HIPC was performed by not only computer simulation but also numerical approximation method which was derived for a single server multi-queue system with nonexhaustive cyclic service. The approximation results are almost same with that of computer simulation. The TDX-10 basic callscenario was applied to the HIPC netowrk and analyzed. these results were compared with TDX-10 IPC and shows that the difference of th emean waiting time in the TX buffer of NTP node increases sharply according to the increase of the message arrival rate.

in this paper, the propagation characteristics of the dominant modes in multiple coupled microstrip lines on a magnetized ferrite substrate are analyzed. The propagation constants and characteristic impedances are calculated by using the spectral domain method. With the numerical results, multi-port impedance parameters as well as scattering parameters are derived from nonreciprocal transmission line equations which are consistent with conventional transmission line theory. In additon, the numerical resutls of nonreciprocal characteristics for various values of structural, material parameters, and external magnetic fields are also presented.

planar circulator swith arbitrarily shaped ferrite resonators are analyzed in this paper. First, resonant frequencies and field distributions for the magnetized ferrite resonator are obtained using finite element method (FEM). Then the RF voltage distributions and other circuit parameters of the circulator which is formed by connecting three suitable transmission lines ot the ferrite resonator are derived from the green function . To remove the spurious solutions in analyzing the ferrite resonator, the results of eigenvalue analysis by node based FEM are comapred with the edge based fEM. The green function is expanded in terms of normalized eigenfunctions of th ecorresponding wave equation. Circulator parameters for circular disk resonator are clculated and compared with the analytical results. The experimental data for the designed circulator using hexagonal reosnator in the 850 MHz frequency range agree well iwth the simulated data.

The far-zone scattered field patterns of a hyperbolic reflector antenna are analyzed by using uniform geometrical theory of diffraction(UTD). The main objective of this paper is to obtain the higher order diffraction contributions which provide the continuity over the shadow boundaries of the first order solution. to obtain the scattered magnetic field characteristics, the scattered field components of the secodn-order diffraction, diffraction-reflection, diffraction-reflection-diffraction terms are added to the result of the previous research. The results of the present research are compared to those of the first order solution and the method of moments. One can observe the improvemtn of the current approach over the first order solution. also, the results of the present method agree very well with those of the moment methods especially in the transition regions near the first order diffraction shadow boundaries.

The purpose of this paper is to analyze the field distribution and the current distribution of leaky coaxial cable with the finite difference-tiem domain(FDTD) algorithm. finite difference equations of maxwell's equations are defined in cylindrical coordinate systems. To simulate the unbounded problem like a free space, the Mur's absorbing boundary conditon is also used. After modeling the leaky coaxial cable with the three dimensional grid structure, the transient resoponse of th efield distribution and the current distribution are depicted in the time domain.

Use of a rapid thermal annealing (RTA) technique is shown to improve the properties of metal-ferroelectric BaMgF$_{4}$-silicon structures. The fluoride film was deposited in an ultra-high vacuum system at asubstrate temperature of 300$^{\circ}C$. A post-deposition annelaing was conducted for 10 seconds at 600.deg. C in a vacuum of 0.1 Torr, using a home-made RTA apparatus. The results showed that the resistivity of the ferroelectric BaMgF$_{4}$ film from a typical value of 1-2${\times}10^{11}{\Omega}{\cdot}cm$ before the annealing to about 5${\times}10^{13}{\Omega}{\cdot}cm$ and reduce the interface state density of the BaMgF$_{4}$/Si interface to about 8${\times}10^{10}cm^{2}{\cdot}$eV. Ferroelectric hysteresis measurements using a sawyer-tower circuit yielded remanent polarization and coercive field values of about 0.5$\mu$C/cm$^{2}$ and 80 kV/cm, respectively. the typical remanent polarization of the BaMgF$_{4}$ films ont he (100) and (111) oreientated silicon wafers were 0.5 - 0.6 $\mu$C/cm$^{2}$ and that of th efilms on the (110) wafers was 1.2$^{\circ}C$/cm$^{2}$.

A semiconductor process imulator operated in windows$^{TM}$ environment has been developed. two-dimensional process simulation in personal computer has been enabled due to the improvement of CPU speed and the efficient use of memory. The process simulator in this paper is capable of calculating diffusion, oxidation, ion implantation, etching and deposition in two-dimensional manner. In addition, graphic-user-friendly editor, parser, and multi-dimensional graphical routine is also available in the devloped simulator.

The .mu.c-Si:H films have been deposited by PeCVD at the various conditions such as hydrogen dilution ratio, substrate temperature and RF power density. Then, we studied their electrical and optical properties. Top gate hydrogenated micro-crystalline silicon thin film transistors($\mu$c-Si:H TFTs) using $\mu$-Si:H and a-SiN:H films have been fabricated by FECVD. The electrical characteristics of the devices have been investigated by semiconductor parameter analyzer and compared with amorphous silicon thin film transistors (a-Si:H TFTs). In this study, on/off current ratio, threshold voltage and the field effect mobility of the $\mu$c-Si:H TFT were $3{\times}10^{4}$, 5.06V and 0.94cm$^{2}$Vs, respectively.

In this paper, we introduced the BQBPH method for making the grating of high efficiency which was improtant in implementing optical PS. The pattern of graing was obtianed by computer simulations using iterative method, and the diffraction efficeincy of designed grating was about 67% through BPM simulation. The grating was fabricated by laser beam writer, and the diffraction efficiency BPM simulation. The grating was fabricated by laser beam writer, and the diffraction efficiency was 47%. We implemented the optical PS with the grating and showed that optical experimental output patterns were good agreement with PS output patterns and first order was main diffraction order.

The pixelated phase grating has been studied as a kind of diffraction gratings splitting and input beam into multiple spots. It consists of regular size cells which produce phase delays, and each cell provokes the phase delay up to sixteen levels. We have compared and analyzed the characteristics of multi-level phase gratings, laying streess on efficiency and resulted pattern. Experimental resutls obtained form fabricated grating have been presented, and the real-time method using a liquid-crystal spatial light modulator has been demonstrated through experiments. Gratings making meams with specific intensities have been designed and optical images have been generated by them. In order to specific intensities have been designed and optical images have been genrated by them. In order to decide the phase delay of each cell, optimization conditon consists of diffraction efficiency and target values. One period of phase gratings fabricated with surface relief was less than 256${\mu}m{\times}256{\mu}m$ and size of each cell was 1${\mu}m{\times}1{\mu}m$ surface relief grating has been made by coating photoresist on the glass plate, writing information pattern by Ar laser and developing it. in the experiment for real-tiem processing liquid-crystal display of epson video projector has been used.

It is shown that a simple vector analysis method can provide beam cone shapes for laser bemas non-paraxially input to dielectric boundaries with inclination. Acceptance coen shapes for angled-endface fibers are calculated by the method. Beam cone shapes inside InP substrates are also calculated by the method for the coupling of an optical fiber and an InP-based photodiode using a Si v-groove. The effectiveness and errors of the recently suggested matrix method for inclined boundaries are also studied.

We propose the concept of incident angle of complex number and analyze planar optical waveguides by applying the concept. The incident angle of complex number is concerned with the modeling of prism-gap-waveguide structures. It is shown that, when optical waveguides are analyzed by use of the transfer matrix method, the proposed concept enable us to find solutions faster and more accurately than ghatak's method which introduces the leaky structure.

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.

In the paper, QCELP (qualcomm code excited linear predictive), CDMA (code division multiple access)'s vocoder algorithm, was analyzed. And then, a ptich parameter seaarch architecture for 16-bit programmable DSP(digital signal processor) for QCELP was designed. Because we speed up the parameter search through high speed DSP using two MACs, we can satisfy speech codec specifiction for the digital celluar. Also, we implemented in FIFO(first-in first-out) memory using register file to increase the access time of data. This DSP was designed using COMPASS, ASIC design tool, by top-down design methodology. Therefore, it is possible to cope with rapid change at mobile communication market.

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

In this paper, we propose a symmetrical pseudo faulty processing elements genration technique to improve the overall reliability of arrays with fixed hardware resources on the fault tolerant VLSI arrays based on single-track switches. We have analyzed the reliability of fault tolerant VLSI arrays and designed control logic for real-tiem reconfiguration. Applying this technique to reconfiguration of VLSI 2-D arrays, we have found that the proposed scheme achieves a higher reliability than the previus methods of similar condition. And we have found that the results of reliability analyzed by mathematic computation are very close to simulated ones. Furthermore, the time overhead for reconfiguration is independent of the array size because the control for reconfiguration is distributively executed by each processing elements. And the proposed scheme has an advantage which maintained properties of VLSI arrays by keeping the locality of interconnections as high as possible even after the reconfiguration.

This paper describes CAD tools for the construction of image database in IC chip analysis CAD system. For IC chip analysis by high-resolution microscopy, the image database is essential to manage more than several thousand images. But manual database construction is error-prone and time-consuming. In order to solve this problem, we develop a set of CAD toos that include image grabber to capture chip images, image editor to make the whole chip image database from the grabbed images, and image divider to reconstruct the database that consists of evenly overlapped images for efficient region search. we also develop an interactive pattern matching method for user-friendly image editing, and a heuristic region search method for fast image division. The tools are developed with a high-performance graphic hardware with JPEG image comparession chip to process the huge color image data. The tools are under the field test and experimental resutls show that the database construction time can be redcued in 1/3 compared to manual database construction.

A CMOS comparator is designed for low voltage and low power operations. The proposed comparator consists of a preadmplifier followed by a regenerative latch. The preasmplifier reduces the power consumption to a half with the power-down mode and the dynamic offsets of the latch, which is affected by each device mismatch, is statistically analyzed. The circuit is designed and simulated using a 0.8.mu.m n-well CMOS process and the dissipated power is 0.16mW at a 20MHz clock speed based on a 3V supply.