A Design of Frequency Synthesizer using Programmable Frequency Divider with Novel Architecture

새로운 구조의 주파수 분주기를 이용한 주파수 합성기 설계

This paper describes the design of a CMOS frequency synthesizer using programmable frequency divider with novel architecture. A novel architecture of programmable divider can be producted all of integer-N and fabricated by 0.65$\mu\textrm{m}$ 2-poly, 2-metal CMOS technology. Frequency synthesizer is simulated by 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS technology. This circuit has settling time of 1.5${\mu}\textrm{s}$ and power consumption of 70㎽. Operating frequency of the frequency synthesizer is 820MHz∼l㎓ with a 2.5V supply voltage.