• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.1
• /
• pp.151-157
• /
• 2013

In this paper, a comparative analysis of PBTI induced device degradation in nanowire n-channel junctionless and inversion mode Multiple-Gate MOSFET(MuGFETs) has been performed. It has been observed that the threshold voltage is increased after PBTI stress and the threshold voltage variation of junctionless device is less significant than that of inversion mode device. However the degradation rate of junctionless device is less significant than that of inversion mode device. The activation energy of the device degradation is larger in inversion mode device than junctionless device. In order to analyze the more significant PBTI induced device degradation in inversion mode device than junctionless device, 3-dimensional device simulation has been performed. The electron concentration in inversion mode device is equal to the one in junctionless device but the electric field in inversion mode device is larger than junctionless device.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.1
• /
• pp.135-141
• /
• 2014

In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.9
• /
• pp.2133-2138
• /
• 2013

In this paper, the variation of a steep subthreshold slope at elevated temperature in nanowire n-channel junctionless and inversion mode MuGFETs has been compared. It has been observed that the subthreshold slopes are increased with the increase of the operation temperature in junctionless and inversio-mode transistors. The variation of a subthreshold slope with operation temperature is more significant in junctionless transistor than inversion-mode transistor. The temperature dependence on the variation of a subthreshold slope for different fin widths shows a similar behavior regardless of fin width. From the temperature dependence on the variation of a subthreshold slope for different substrate biases, it has been observed that the variation of a subthreshold slope is less significant when the substrate bias was applied. It is worth noting that one can achieve a subthreshold slope of below 41mV/dec at elevated temperature of 400K using the junctionless MuGFETs with a positive substrate bias.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.4
• /
• pp.785-792
• /
• 2012

In this paper, a current-voltage characteristics of n-channel junctionless and inversion mode(IM) MuGFET, and p-channel junctionless and accumulation mode(AM) MuGFET has been measured and analyzed for the application in high speed and low power switching devices. From the variation of the threshold voltage and the saturation drain current with the substrate bias voltages, their variations in IM devices are larger than junctionless devices for n-channel devices, but their variations in junctioness devices are larger than AM devices for p-channel devices. The variations of transconductance with substrate biases are more significant in p-channel devices than n-channel devices. From the characteristics of subthreshold swing, it was observed that the S value is almost independent on the substrate biases in n-channel devices and p-channel junctionless devices but it is increased with the increase of the substrate biases in p-channel AM devices. For the application in high speed and low power switching devices using the substrate biases, IM device is better than junctionless devices for n-channel devices and junctionless device is better than AM devices for p-channel devices.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.8
• /
• pp.1885-1890
• /
• 2013

In this paper, the electrical properties of nanoscale junctionless p-channel MuGFET at cryogenic temperature have been analyzed experimentally. The experiment was performed using a cryogenic probe station which uses the liquid Helium. It has been observed that the drain current oscillation at low drain voltage and cryogenic temperature was more pronounced in junctionless transistor than in accumulation mode transistor. The reason for more marked oscillation is due to the smaller electrical cross section area of the inversion channel which is formed at the center of silicon film in junctionless transistor. It was also observed that the drain current and maximum transconductance were increased as the measurement temperature increased. This is resulted from the increase of hole mobility and the decrease of the threshold voltage as the measurement temperature increases. The drain current oscillation due to the quantum effects can be occurred up to the room temperature when the device size scales down to the nanometer level.

• Journal of Korean Society of Steel Construction
• /
• v.23 no.5
• /
• pp.547-555
• /
• 2011

An unstiffened top and seat angle connection is a type of partially restrained connection that is suitable for low- and medium-rise steel buildings. The plastic moment resisting capacity of such connection is needed in practical design, in addition to the accurate prediction of the initial rotational stiffness. Therefore, most of the studies conducted for the mentioned connections were performed to predict the initial stiffness and the plastic moment resisting capacity with varying geometric properties. The main parameters of such experimental tests were the thickness and high-strength bolt gauge distance of AISC LRFD-type A top and seat angle connections. Based on the test results, the analytical model was also proposed in this study. The applicability of the proposed model was verified by comparing the test results from this study with those of other studies.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.18 no.7
• /
• pp.1657-1662
• /
• 2014

In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{\times}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.789-794
• /
• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.9
• /
• pp.1627-1634
• /
• 2017

In this work, a junctionless transistor with different film thickness of amorphous InGaZnO has been fabricated and it's instability has been analyzed with different film thickness under positive and negative gate stress as well as light illumination. It was found that the threshold voltage shift and the variation of drain current have been increased with decrease of film thickness under the condition of gate stress and light illumination. The reasons for the observed results have been explained by stretched-exponential model and device simulation. Due to the reduced carrier trapping time with decrease of film thickness, electrons and holes can be activated easily. Due to the increase of vertical channel electric field reaching the back interface with decrease of film thickness, more electrons and holes can be accumulated in back interface. When one decides the film thickness for the fabrication of junctionless transistor, the more significant device instability with decrease of film thickness should be consdered.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.1
• /
• pp.117-124
• /
• 2018

Junctionless amorphous InGaZnO thin film transistors with different film thickness have been fabricated. Their device performance parameters were extracted and gate oxide breakdown voltages were analyzed with different film thickness. The device performances were enhanced with increase of film thickness but the gate oxide breakdown voltages were decreased. The device performances were enhanced with increase of temperatures but the gate oxide breakdown voltages were decreased due to the increased drain current. The drain current under illumination was increased due to photo-excited electron-hole pair generation but the gate oxide breakdown voltages were decreased. The reason for decreased breakdown voltage with increase of film thickness, operation temperature and light intensity was due to the increased number of channel electrons and more injection into the gate oxide layer. One should decide the gate oxide thickness with considering the film thickness and operating temperature when one decides to replace the junctionless amorphous InGaZnO thin film transistors as BEOL transistors.