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http://dx.doi.org/10.6109/jkiice.2014.18.1.135

Device Design Guideline to Reduce the Threshold Voltage Variation with Fin Width in Junctionless MuGFETs  

Lee, Seung-Min (Department of Electronics Engineering, Incheon National University)
Park, Jong-Tae (Department of Electronics Engineering, Incheon National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.18, no.1, 2014 , pp. 135-141 More about this Journal
Abstract
In this paper, the device design guideline to reduce the threshold voltage variation with fin width in junctionless MuGFET has been suggested. It has been observed that the threshold voltage variation was increased with increase of fin width in junctionless MuGFETs. To reduce the threshold voltage variation with fin width in junctionless MuGFETs, 3-dimensional device simulation with different gate dielectric materials, silicon film thickness, and an optimized fin number has been performed. The simulation results showed that the threshold voltage variation can be reduced by the gate dielectric materials with a high dielectric constant such as $La_2O_3$ and the silicon film with ultra-thin thickness even though the fin width is increased. Particularly, the reduction of the threshold voltage variation and the subthreshold slope by reducing the fin width and increasing the fin numbers is known the optimized device design guideline in junctionless MuGFETs.
Keywords
Junctionless MuGFET; threshold voltage variation; subthreshold slope; fin width; high-K dielectrics;
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1 J. P. Colinge, C. W. Lee, A. Afzalian, N. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junction," Nature Nano-technology, vol. 5, no. 3, pp. 225-229, 2010.   DOI   ScienceOn
2 C.W. Lee, I. Ferrain, A. Afzalian, R. Yan, N.D. Akhavan, P. Razzavi, and J.P. Colinge, "Performance estimation of junctionless multigate transistors," Solid-State Electronics, vol.54, pp.97-103, 2010.   DOI   ScienceOn
3 A. Gnudi, S. Reggiani, E. Gnani, and G. Baccarani, "Analysis of threshold voltage variation due to random dopant fluctuation in junctionless FETs," IEEE Electron Device Lett., vol. 33, no.3, pp.336-338, 2012.   DOI   ScienceOn
4 R. D. Trevisoli, R. T. Doria, M. Souza, M.A. Pavanello, "A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors," Solid-State Electonics, to be published in 2013.
5 S. Choi, D. Moon, S. Kim, J.P. Duarte, and Y. Choi, "Sensitivity of threshold voltage to nanowire width variation in junctionless transistors," IEEE Electron Device Lett., vol. 32, no.2, pp.125-127, 2011.   DOI   ScienceOn
6 J.P. Colinge, C.W. Lee, I Ferrain, N. Akhavan, R. Yan, P. Razavi, R. Yu, A. Nazarov, and R.T. Doriac, "Reduced electric field in junctionless transistors, " Applied Physics Letters, vol. 96, p.0773510, 2010.
7 D.Y. Jeon, S. Park, M. Mouis, M. Berthome, S. Barrud, G.T Kim, and G. Ghibaudo, Revisited parameter extraction methodology for electrical characterization of junctionless transistors," Solid-State Electronics, to be published in 2013.
8 G. Leung, and C. Chui, "Variability impact of random dopant fluctuation on nanoscle junctionless FinFETs," IEEE Electron Device Lett., vol. 33, no.6, pp.767-769, 2012.   DOI   ScienceOn
9 A.N. Nazarov, V.S. Lysenko, I. Ferain, S. Das, R. Yu, A. Kranti, N. D. Akhavan, P. Razavi, and J.P. Colinge, "Floating body effects in junctionless MuGFETs," Proceeding of ULSI, 2012, pp.93-94.
10 D. Moon, S. Choi, J.P. Durate, and Y. Choi, "Investigation of silicon nanowire gate-all-around junctioless transistors built on a bulk substrate," IEEE Trans. on Electron Device, vol. 60, no. 4, pp.1355-1360, 2013.   DOI   ScienceOn
11 S Ohmi, C. Kobayashi, K Aizawa, S Yamamoto, E Tokomitsu, H Ishiwara. and H Iwai, "High quality ultrathin $La_2O_3$ for high-K gate insulator," Solid State Device Research Conference, 2001, pp.235-238.