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http://dx.doi.org/10.6109/jkiice.2012.16.4.785

Current-Voltage Characteristics with Substrate Bias in Nanowire Junctionless MuGFET  

Lee, Jae-Ki (가천대학교 전자공학과)
Park, Jong-Tae (인천대학교 전자공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.16, no.4, 2012 , pp. 785-792 More about this Journal
Abstract
In this paper, a current-voltage characteristics of n-channel junctionless and inversion mode(IM) MuGFET, and p-channel junctionless and accumulation mode(AM) MuGFET has been measured and analyzed for the application in high speed and low power switching devices. From the variation of the threshold voltage and the saturation drain current with the substrate bias voltages, their variations in IM devices are larger than junctionless devices for n-channel devices, but their variations in junctioness devices are larger than AM devices for p-channel devices. The variations of transconductance with substrate biases are more significant in p-channel devices than n-channel devices. From the characteristics of subthreshold swing, it was observed that the S value is almost independent on the substrate biases in n-channel devices and p-channel junctionless devices but it is increased with the increase of the substrate biases in p-channel AM devices. For the application in high speed and low power switching devices using the substrate biases, IM device is better than junctionless devices for n-channel devices and junctionless device is better than AM devices for p-channel devices.
Keywords
Junctionless MuGFET; Inversion mode MuGFET; Accumulation mode MuGFET; Substrate bias effect;
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1 T. Ohtou, K. Yokoyama, K. Shimizu, T. Nagumon, and T. Hiramoto, "Threshold voltage control of AC performance deg- radation free FD SOI MOSFET with extremely thin box using variable body factor scheme," IEEE Trans Elec- tron Devices vol. 54, no. 2, pp. 301-307, 2007   DOI   ScienceOn
2 J. B. Kuo, W. C. Lee, and J. H. Sim, "Back-gate bias effects on the sub- threshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 77 and 300K," IEEE Trans Electron Devices vol. 39, no. 12, pp. 2781-2790, 1992   DOI   ScienceOn
3 J.P. Colinge, Silicon-on-Insulator tech- nology: materials to VLSI, 2nd editon, Nor-well, MA Kluwer, 1997
4 K. Tokunaga, and J. C. Sturn, "Substrate bias dependence of subthreshold slopes in ully depleted Silicon-on-Insulator MOS- FETs," IEEE Trans Electron Devices vol. 38, no.8, pp. 1803-1807, 1991   DOI   ScienceOn
5 Jong Tae Park, and J. P. Colinge, "Multiple gate SOI MOSFETs :Device design guidelines," IEEE Trans. Electron Device, vol. 49, no,12, pp. 2222-2228, 2002   DOI   ScienceOn
6 J. P. Colinge, "Multiple-gate SOI MOS- FETs," Solid-State Electronics, vol. 48, no. 6, pp. 897-905, 2004   DOI   ScienceOn
7 http://newsroom.intel.com/docs/DOC-2032
8 M. Masahara, K .Endo, Y. Liu, T. Mats- ukawa, S. Ouchi, K. Ishii, E. Sugimata, E. Suzuki, "Demostration and analysis of accumulation-mode double-gate metal oxide semiconductor field effect tran- sistor," Jpn J. Appl. Phys., vol. 45, no. 4b, pp. 079-3083, 2006   DOI
9 J. P. Colinge, C. W. Lee, A. Afzalian, N. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junction," Nature Nano-technology, vol. 5, no. 3, pp. 225-229, 2010   DOI   ScienceOn
10 J. P. Raskin, J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. Dehdashti, R. Yan, P. razavi, R. Yu, "Mobility improvement in nanowire junctionless transistors by uniaxial strain," Appl. Phys. lett., vol. 97, pp. 042114, 2010   DOI   ScienceOn
11 C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, J. P. Colinge, "Performance estimation of junctionless multiple gate transistors," Solid-State Electronics, vol. 54, no. 2, pp. 97-103, 2010   DOI   ScienceOn