1 |
T. Ohtou, K. Yokoyama, K. Shimizu, T. Nagumon, and T. Hiramoto, "Threshold voltage control of AC performance deg- radation free FD SOI MOSFET with extremely thin box using variable body factor scheme," IEEE Trans Elec- tron Devices vol. 54, no. 2, pp. 301-307, 2007
DOI
ScienceOn
|
2 |
J. B. Kuo, W. C. Lee, and J. H. Sim, "Back-gate bias effects on the sub- threshold behavior and the switching performance in an ultrathin SOI CMOS inverter operating at 77 and 300K," IEEE Trans Electron Devices vol. 39, no. 12, pp. 2781-2790, 1992
DOI
ScienceOn
|
3 |
J.P. Colinge, Silicon-on-Insulator tech- nology: materials to VLSI, 2nd editon, Nor-well, MA Kluwer, 1997
|
4 |
K. Tokunaga, and J. C. Sturn, "Substrate bias dependence of subthreshold slopes in ully depleted Silicon-on-Insulator MOS- FETs," IEEE Trans Electron Devices vol. 38, no.8, pp. 1803-1807, 1991
DOI
ScienceOn
|
5 |
Jong Tae Park, and J. P. Colinge, "Multiple gate SOI MOSFETs :Device design guidelines," IEEE Trans. Electron Device, vol. 49, no,12, pp. 2222-2228, 2002
DOI
ScienceOn
|
6 |
J. P. Colinge, "Multiple-gate SOI MOS- FETs," Solid-State Electronics, vol. 48, no. 6, pp. 897-905, 2004
DOI
ScienceOn
|
7 |
http://newsroom.intel.com/docs/DOC-2032
|
8 |
M. Masahara, K .Endo, Y. Liu, T. Mats- ukawa, S. Ouchi, K. Ishii, E. Sugimata, E. Suzuki, "Demostration and analysis of accumulation-mode double-gate metal oxide semiconductor field effect tran- sistor," Jpn J. Appl. Phys., vol. 45, no. 4b, pp. 079-3083, 2006
DOI
|
9 |
J. P. Colinge, C. W. Lee, A. Afzalian, N. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junction," Nature Nano-technology, vol. 5, no. 3, pp. 225-229, 2010
DOI
ScienceOn
|
10 |
J. P. Raskin, J. P. Colinge, I. Ferain, A. Kranti, C. W. Lee, N. Dehdashti, R. Yan, P. razavi, R. Yu, "Mobility improvement in nanowire junctionless transistors by uniaxial strain," Appl. Phys. lett., vol. 97, pp. 042114, 2010
DOI
ScienceOn
|
11 |
C. W. Lee, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, J. P. Colinge, "Performance estimation of junctionless multiple gate transistors," Solid-State Electronics, vol. 54, no. 2, pp. 97-103, 2010
DOI
ScienceOn
|