Electrical characteristics of polysilicon thin film transistors with PNP gate

PNP 게이트를 가지는 폴리 실리콘 박막 트랜지스터의 전기적 특성

One of the major problems for poly-Si TFTs is the large off state leakage current. LDD (lightly doped drain) and offset gated structures have been employed in order to reduce the leakage current. However, these structures also redcue the oN current significantly due to the extra series resistance caussed by the LDD or offset region. It is desirable to have a device which would have the properties of the offset gated structure in the OFF state, while behaving like a fully gated device in the oN state. Therefore, we propose a new thin film transistor with pnp junction gate which reduce the leakage curretn during the OFF state without sacrificing the ON current during the ON state.