• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• 대한전자공학회논문지SD
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• 제48권10호
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• pp.54-61
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• 2011

본 논문에서는 intrinsic-body cylindrical/surrounding gate SOI MOSFET의 I-V 특성 도출을 위한 간단한 해석적 모델을 제시하였다. Intrinsic 실리콘 채널 영역에서의 Poisson 방정식과 gate oxide 내에서의 Laplace 방정식을 해석적으로 풀어 소스와 드레인 양단 끝에서의 표면 전위 분포를 bisection method를 이용하여 구하였다. 구해진 표면 전위를 바탕으로 closed-form의 I-V 특성 식을 도출하였다. 도출된 I-V 특성 표현 식을 모의 실험한 결과, 소자의 parameter와 가해진 bias 전압에 대한 비교적 정확한 의존성을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.92-97
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• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.111-120
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• 2011

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

• 전기전자학회논문지
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• 제22권1호
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• pp.74-79
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• 2018

본 논문에서는 무접합 원통형과 무접합 이중게이트 MOSFET의 중심전위와 문턱전압이하 스윙의 관계를 분석하였다. 해석학적 전위분포를 이용하여 문턱전압이하 스윙을 구하고 중심전위와 문턱전압이하 스윙을 채널크기 변화에 따라 비교 고찰하였다. 결과적으로 중심전위분포의 변화가 직접적으로 문턱전압이하 스윙에 영향을 미치고 있다는 것을 관찰하였다. 채널두께나 산화막 두께가 증가할수록 문턱전압이하 스윙은 증가하였으며 JLDG 구조가 더욱 민감하게 증가하였다. 그러므로 나노구조 MOSFET의 단채널효과를 감소시키기 위하여 JLCSG 구조가 더욱 효과적이라는 것을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.221-226
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• 2008

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.