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http://dx.doi.org/10.5370/JEET.2014.9.6.2079

Analytical Threshold Voltage Modeling of Surrounding Gate Silicon Nanowire Transistors with Different Geometries  

Pandian, M. Karthigai (Dept. of Electronics and Communication Engineering, Pandian Saraswathi Yadav Engineering College)
Balamurugan, N.B. (Dept. of Electronics and Communication Engineering, Thiagarajar College of Engineering)
Publication Information
Journal of Electrical Engineering and Technology / v.9, no.6, 2014 , pp. 2079-2088 More about this Journal
Abstract
In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.
Keywords
Junction Based Cylindrical Surrounding Gate (JBCSG) silicon nanowire transistor; Rectangular surrounding gate silicon nanowire transistor; Threshold voltage; Parabolic approximation; silicon thickness; Channel Length; drain Bias;
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1 Yuting Wan, Jian Sha, Bo Chen, Yanjun Wang, Zongli Wang and Yewu Wang, "Nanodevices based on Silicon Nanowires", Recent Patents on Nanotechnology, Vol. 3, Issue. 1, pp. 1-9, January 2009.
2 B. Yu, W.Y. Lu, H. Lu and Y. Taur, "Analytic Charge Model for Surrounding Gate MOSFETs", IEEE Transactions on Electron Devices, Vol. 54, Issue. 3, pp. 492-496, March 2007.   DOI   ScienceOn
3 D.Jimenez, J.J. Saenz, B. Iniguez, J.Sune, L.F. Marsal and J. Pallares, "Modeling of Nanoscale GAA MOSFETs", IEEE Electron Device Lett., Vol. 25, Issue. 5, pp. 314-316, May 2004.   DOI   ScienceOn
4 D. Jimenez, B. Iniguez, J. Sune, L.F. Marsal and J. Pallares, "Continuous Analytic I-V model for Surrounding Gate MOSFETs", IEEE Electron Device Lett., Vol.25, Issue.8, pp.571-573, August 2004.   DOI   ScienceOn
5 H. Borli, S. Kolberg, T.A. Fjeldly, and B. Iniguez, "Precise Modeling Framework for short channel Double-Gate and GAA MOSFETs", IEEE Transactions on Electron Devices, Vol.55, Issue.10, pp. 2678-2686, October 2008.   DOI   ScienceOn
6 C. P. Auth and James D. Plummer, "Scaling theory for Cylindrical, Fully depleted, Surrounding Gate MOSFETs", IEEE Electron Device Lett., Vol. 18, Issue. 2, pp. 74-76, February 1997.   DOI   ScienceOn
7 FJG Ruiz, IM Tienda-Luna, A.Godoy, L. Donetti and F. Gamiz, "A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison with Double Gate MOSFETs", IEEE Transactions on Electron Devices, Vol. 57, Issue. 10, pp. 2477-2483, October 2010.   DOI   ScienceOn
8 E. Gnani, A. Gnudi, S. Reggiani and G. Baccarani, "Quasi Ballistic Transport in Nanowire FETs", IEEE Transactions on Electron Devices, Vol. 55, Issue. 11, pp. 2918-2930, November 2008.   DOI   ScienceOn
9 E.Gnani, A.Gnudi, M.Luisier and G.Baccarani, "Band effects on Transport Characteristics of Ultrascaled Nanowire FETs", IEEE Transactions on Nanotechnology, Vol.7, Issue.6, pp.700-709, November 2008.   DOI   ScienceOn
10 S.Poli, M.Pala and T.Poiroux, "Full Quantum Tratment of Remote Coulomb Scattering in Silicon Nanowire FETs", IEEE Transactions on Electron Devices, Vol. 56, Issue. 6, pp. 1191-1198, June 2009.   DOI   ScienceOn
11 T. Poiroux, M. Vinet, O. Faynot, J. Wildeiz, J. Lolivier, T.Ernst, B.Previtali and S.Delonibus, "Multiple Gate Devices :Advantages and Challenges", Microelectronic Engineering, Vol.80, pp. 378-385, June 2005.   DOI   ScienceOn
12 J.P. Collinge, M.H. Gao, A. Romano, H. Maes and C. Claeys, "Silicon-On-Insulator Gate-All-Around Device", IEDM Tech. dig., 1990, pp.595-599.
13 N.Singh, F.Y.Lim, W.W. Fang et.al, "Ultra Narrow Silicon Nanowire GAA CMOS Devices: Impact of Diameter, Channel Orientation and Low Temperature on Device Performance", IEDM Tech. dig., 2006, pp. 547-550.
14 S. Oh, D. Monroe and JM. Hergenrother, "Analytic Description of Short channel effects in Fully Depleted Double Gate and Cylindrical Surrounding Gate MOSFETs", IEEE Transactions on Electron Devices, Vol. 21, Issue. 9, pp. 445-447, September 2000.   DOI   ScienceOn
15 D. Jimenez, B. Iniguez, J. Sune and J. J. Saenz, "Analog Performance of the Nanoscale Double Gate MOSFET near the Ultimate Scaling Limits", J. App. Physics., Vol.96, Issue.9, pp. 5271-5276, November 2004.   DOI   ScienceOn
16 Christoper. P. Auth and James D. Plummer, "A Simple Model for Threshold Voltage of Surrounding- Gate MOSFETs", IEEE Transactions on Electron Devices, Vol. 45, Issue.11, pp.2381-2383, November 1998.   DOI   ScienceOn
17 Chiang Te-Kuang, "A Compact Analytical Threshold- Voltage Model for Surrounding-Gate MOSFETs with Interface Trapped Charges", IEEE Electron Device Letters, VOL. 31, Issue. 8, pp. 788-790, August 2010.   DOI   ScienceOn
18 Chiang Te-Kuang, "A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs with Localized Interface Trapped Charges", IEEE Transactions on Electron Devices, Vol. 58, Issue. 2, pp. 567-571, February 2011.   DOI   ScienceOn
19 M. Jagadesh Kumar, Ali A. Orouji, and Harshit Dhakad, "A New Dual-Material SG Nanoscale MOSFET: Analytical Threshold-Voltage Model", IEEE Transactions on Electron Devices, Vol. 53, Issue.4, pp. 920-923, April 2006.   DOI   ScienceOn
20 Chiang Te-Kuang, "A New Quasi-2-D Threshold Voltage Model for Short-Channel Junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs", IEEE Transactions on Electron Devices, Vol. 59, Issue. 11, pp. 3127-3129, November 2012.   DOI   ScienceOn
21 Chiang Te-Kuang, "A New Quasi-2-D Threshold Voltage Model for Short-Channel Junctionless Double Gate MOSFETs", IEEE Transactions on Electron Devices, Vol. 59, Issue. 9, pp. 2284-2289, September 2012.   DOI   ScienceOn
22 Z.Ghoggali, F.Djeffal, M.A.Abdi et.al., "An Analytical Threshold Voltage Model for Nannoscale GAA MOSFETs including effects of Hot Carrier Induced Interface Charges", Design and Test Workshop, IDT 2008, pp.93-97, December 2008.
23 Yu-sheng Wu and Pin Su, "Quantum confinement Effects in short channel GAA MOSFETs and its impact on the sensitivity of Threshold Voltage to Process Variations", Proceedings of IEEE International Conference on SOI, pp.1-2, October 2009.
24 B Ray and Santanu Mahapatra, "Modeing and Analysis of Body Potential of Cylindrical GAA Nanowire Transistor", IEEE Transactions on Electron Devices, Vol. 55, Issue. 9, pp. 2409-2416, September 2008.   DOI   ScienceOn
25 L.De Mechielis, L.Selmi and AM.Lonescu, "A Quasi Analytical model for Nanowire FETs with Arbitrary Polygonal Cross Section", Solid State Electronics, Vol.54, Issue.9, September 2010.
26 P. Rakesh Kumar and S. Mahapthra, "Quantum threshold voltage modeling of short channel quad gate silicon nanowire transistor", IEEE Transactions on Nanotechnology, Vol. 10, No.1, January 2011.
27 Biswajit Ray and Santanu Mahapatra, "A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor" 21st International Conference on VLSI Design, 2008, pp. 447-452, VLSID 2008.
28 B. Iniguez, D. Jimenez, J.Roig, H. A. Hamid, L. F. Marsal and J. Pallares, "Explicit Continuous model for Long Channel undoped Surrounding Gate MOSFETs", IEEE Transactions on Electron Devices, Vol. 52, Issue. 8, pp. 1868-1873, August 2005.   DOI   ScienceOn