JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation

  • Vanitha, P. (Department of Electronics and Communication Engineering, Sethu Institute of Technology) ;
  • Balamurugan, N.B. (Department of Electronics and Communication Engineering, Sethu Institute of Technology) ;
  • Priya, G. Lakshmi (Department of Electronics and Communication Engineering, Sethu Institute of Technology)
  • Received : 2014.10.29
  • Accepted : 2015.08.08
  • Published : 2015.12.30
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Abstract

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

Keywords

References

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