• 전기학회논문지
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• 제58권1호
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.582-594
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• 2016

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.125-128
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• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• 한국산학기술학회논문지
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• 제8권2호
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• pp.201-206
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• 2007

본 논문에서는 NoC(Network-on Chip) 구조로 구현된 core-based 시스템에 대한 효율적인 저전력 테스트 방법을 제안한다 NoC의 라우터 채널로 전송되는 테스트 데이터의 전력소모를 줄이기 위해서 스캔 벡터들을 채널 폭만큼의 길이를 갖는 flit으로 분할하고 nit간 천이율(switching rate)이 최소화 되도록 don't care 입력을 할당하였다. ISCAS 89 벤치마크에 대하여 실험을 한 결과, 제안된 방법은 약 35%의 전력 감소를 나타내었다.

• 전자공학회논문지 IE
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• 제45권3호
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• pp.5-12
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• 2008

디지털 논리회로의 테스트 데이터와 전력소비를 단축시킬 수 있는 효율적인 테스트 방법을 제안한다. 제안 하는 테스트 방법은 테스트장비내의 테스트 데이터 저장 공간을 줄이는 하이브리드 run-length 인코딩 벙법에 기초하고, 수정된 Bus-invert 코딩 방법과 스캔 셀 설계를 제안하여, 스캔 동작시의 개선된 전력 단축효과를 가져온다. ISCAS'89 벤치마크 회로의 실험결과 고장 검출율의 저하 없이 평균 전력은 96.7%, 피크전력은 84%의 단축을 보이며 테스트 데이터는 기존 방법보다 78.2%의 압축을 갖는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• 대한전자공학회논문지SD
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• 제45권6호
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• pp.43-48
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• 2008

일반적으로 자체 테스트 동작은 입력 벡터들 사이에 상호 연관성이 없기 때문에 더 많은 전력을 소비하는 것으로 알려져 있다. 이러한 점은 회로에 손상을 유발할 뿐 아니라 배터리 수명에도 악영향을 미치기 때문에 반드시 해결되어야 할 과제 중 하나이다. 이를 위해 본 논문에서는 새로운 방식의 BIST(Built-In Self Test) 구조를 제안하여 테스트 동작에서의 천이를 감소시키고, 이를 통해 전력소모를 줄이고자 한다. 제안하는 구조에서는 LFSR(Linear Feedback Shift Register)을 통해 생성되는 pseudo-random 테스트 벡터가 스캔 경로로 들어가기 전에 3 bit씩 모아 더 적은 천이를 가지는 4 bit의 패턴으로 변형한다. 이러한 변형과 그에 대한 복원 과정은 기존의 스캔 BIST 구조에서 Bit Generator와 Bit Dropper라는 모듈을 추가하여 간단히 구현하였다. 제안하는 구조를 ISCAS'89 benchmark 회로에 적용한 결과 약 62%의 천이 감소를 확인하였고 이를 통해 제안하는 구조의 효율성을 검증하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.463-469
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• 2016

This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS'89 and ITC'99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.104-110
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• 2006

오늘날 시스템 온 칩 테스트에 있어서 많은 양의 테스트 데이터, 시간 및 전력 소모는 매우 중요한 문제이다. 이러한 문제들을 해결하기 위해서 본 논문은 새로운 테스트 데이터 압축 기술을 제안한다. 우선, 테스트 큐브 집합에 있는 돈 캐어 비트에 저전력 테스트를 위한 비트할당을 한다. 그리고, 비트할당이 된 저전력 테스트 데이터의 압축효율을 높이기 위해 이웃 비트 배타적 논리합 변환을 사용하여 변환한다. 최종적으로, 변환된 테스트 데이터는 효과적으로 압축됨으로써 테스트 장비의 저장공간과 테스트 데이터 인가시간을 줄일 수 있게 된다.