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Verification of System using Master-Slave Structure  

Kim, In-Soo (성균관대학교 정보통신공학부)
Min, Hyoung-Bok (성균관대학교 정보통신공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.58, no.1, 2009 , pp. 199-202 More about this Journal
Abstract
Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.
Keywords
Low Power Testing; Master-Slave Structure; Scan Design; Shift Operation; System Verification;
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