JSTS:Journal of Semiconductor Technology and Science

  • 제16권4호
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  • Pages.463-469
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  • 2016
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Compression-Friendly Low Power Test Application Based on Scan Slices Reusing

  • Wang, Weizheng (Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation, Changsha University of Science and Technology) ;
  • Wang, JinCheng (Hunan Provincial Key Laboratory of Intelligent Processing of Big Data on Transportation, Changsha University of Science and Technology) ;
  • Cai, Shuo (College of computer and communication Engineering, Changsha University of Science and Technology) ;
  • Su, Wei (Modern Education Technology Center, Nanjing Audit University) ;
  • Xiang, Lingyun (College of computer and communication Engineering, Changsha University of Science and Technology)
  • 투고 : 2015.09.28
  • 심사 : 2016.03.14
  • 발행 : 2016.08.30
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초록

This paper presents a compression-friendly low power test scheme in EDT environment. The proposed approach exploits scan slices reusing to reduce the switching activity during shifting for test scheme based on linear decompressor. To avoid the impact on encoding efficiency from resulting control data, a counter is utilized to generate control signals. Experimental results obtained for some larger ISCAS'89 and ITC'99 benchmark circuits illustrate that the proposed test application scheme can improve significantly the encoding efficiency of linear decompressor.

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참고문헌

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