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Reduction of Test Data and Power in Scan Testing for Digital Circuits using the Code-based Technique  

Hur, Yong-Min (Dept. of Computer Software, Dong Seoul College)
Shin, Jae-Heung (Dept. of Digital Broadcasting & Media, Dong Seoul College)
Publication Information
전자공학회논문지 IE / v.45, no.3, 2008 , pp. 5-12 More about this Journal
Abstract
We propose efficient scan testing method capable of reducing the test data and power dissipation for digital logic circuits. The proposed testing method is based on a hybrid run-length encoding which reduces test data storage on the tester. We also introduce modified Bus-invert coding method and scan cell design in scan cell reordering, thus providing increased power saving in scan in operation. Experimental results for ISCAS'89 benchmark circuits show that average power of 96.7% and peak power of 84% are reduced on the average without fault coverage degrading. We have obtained a high reduction of 78.2% on the test data compared the existing compression methods.
Keywords
low power; scan testing; Bus-invert coding; Run-length code; compression;
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