대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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스캔입력 변형기법을 통한 새로운 저전력 스캔 BIST 구조

A New Low Power Scan BIST Architecture Based on Scan Input Transformation Scheme

  • 손현욱 (연세대학교 전기전자공학과) ;
  • 김유빈 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Son, Hyeon-Uk (School of Electrical & Electronic Engineering, Yonsei University) ;
  • Kim, You-Bean (School of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (School of Electrical & Electronic Engineering, Yonsei University)
  • 발행 : 2008.06.25
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초록

일반적으로 자체 테스트 동작은 입력 벡터들 사이에 상호 연관성이 없기 때문에 더 많은 전력을 소비하는 것으로 알려져 있다. 이러한 점은 회로에 손상을 유발할 뿐 아니라 배터리 수명에도 악영향을 미치기 때문에 반드시 해결되어야 할 과제 중 하나이다. 이를 위해 본 논문에서는 새로운 방식의 BIST(Built-In Self Test) 구조를 제안하여 테스트 동작에서의 천이를 감소시키고, 이를 통해 전력소모를 줄이고자 한다. 제안하는 구조에서는 LFSR(Linear Feedback Shift Register)을 통해 생성되는 pseudo-random 테스트 벡터가 스캔 경로로 들어가기 전에 3 bit씩 모아 더 적은 천이를 가지는 4 bit의 패턴으로 변형한다. 이러한 변형과 그에 대한 복원 과정은 기존의 스캔 BIST 구조에서 Bit Generator와 Bit Dropper라는 모듈을 추가하여 간단히 구현하였다. 제안하는 구조를 ISCAS'89 benchmark 회로에 적용한 결과 약 62%의 천이 감소를 확인하였고 이를 통해 제안하는 구조의 효율성을 검증하였다.

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

키워드

참고문헌

  1. Swarup Bhunia, Hamid Mahmoodi, Debjyoti Ghosh, and Kaushik Roy, "Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning," in Proc. of IEEE International Symposium on Quality Electronic Design, pp.435-458, 2005
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  4. Rui Li, Chen Hu, Jun Yang, Zhe Zhang, Youhua Shi, and Longxing Shi, "A New Low Power BIST Methodology by Altering the Structure of Linear Feedback Shift Registers," in Proc. of IEEE ASIC/SOC Conference, pp.646-649, 2001
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