Browse > Article

A New Low Power Scan BIST Architecture Based on Scan Input Transformation Scheme  

Son, Hyeon-Uk (School of Electrical & Electronic Engineering, Yonsei University)
Kim, You-Bean (School of Electrical & Electronic Engineering, Yonsei University)
Kang, Sung-Ho (School of Electrical & Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.6, 2008 , pp. 43-48 More about this Journal
Abstract
Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.
Keywords
Low power BIST; Scan BIST architecture; Power reduction scheme;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Nan-Cheng Lai, Sying-Jyan Wang, and Yu-Hsuan Fu, "Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size," IEEE Trans. Computer -Aided Design of Integrated Circuits and System, Vol. 25, Issue 11, pp. 2586 - 2594, Nov 2006   DOI   ScienceOn
2 Seongmoon Wang, "A BIST TPG for Low Power Dissipation and High Fault Coverage," IEEE Trans. Very Large Scale Integration Systems, Vol. 15, no. 7, July 2007
3 Y.Bonhomme, P.Girard, L.Guiller, C.Landrault, and S.Pravossoudovitch, "A Gated Clock scheme for Low Power Scan Testing of Logic ICs or Embedded Cores," in Proc. of IEEE Asian Test Symposium, pp.253, 2001
4 He Ronghui, Xiaowei, and Gong Yunzhan, "A Low Power BIST TPG Design," in Proc. of IEEE ASIC/SOC Conference, pp.1136-1139, 2003
5 Xiaoding Chen, and Michael S. Hsiao, "An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection," IEEE Trans. Very Large Scale Integration Systems, Vol. 15, no. 4, April 2007
6 Swarup Bhunia, Hamid Mahmoodi, Debjyoti Ghosh, and Kaushik Roy, "Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning," in Proc. of IEEE International Symposium on Quality Electronic Design, pp.435-458, 2005
7 Youbean Kim, Dongsup Song, Kicheol Kim, Incheol Kim and Sungho Kang, "TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure," in Proc. of 15th Asian Test Symposium, pp.17-24, 2006
8 Rui Li, Chen Hu, Jun Yang, Zhe Zhang, Youhua Shi, and Longxing Shi, "A New Low Power BIST Methodology by Altering the Structure of Linear Feedback Shift Registers," in Proc. of IEEE ASIC/SOC Conference, pp.646-649, 2001