References
- P.M. Rosinger, P.T. Gonciari, B.M. Al-Hashimi, and N. Nicolici, 'Analysing trade-offs in scan power and test data compression for systems-on-a-chip', lEE Proc. Comput. Digital Tech, vol. 149, Issue 4, pp. 188-196, July 2002 https://doi.org/10.1049/ip-cdt:20020450
- V. Iyengar and K. Chakrabarty, 'System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints', IEEE Trans. Computer-Aided Design, vol. 21, Issue 9, pp. 1088-1094, Sept. 2002 https://doi.org/10.1109/TCAD.2002.801102
- H. Kilic and L. Oktem, 'Low-power test pattern generator design for BIST via non-uniform ?cellular automata', in Proc. Int Symp. IEEE VLSI Design Auto. Test, pp. 212-215, 2005 https://doi.org/10.1109/VDAT.2005.1500058
- T. Yoshida and M. Watati, 'A new approach for low-power scan testing', in Proc. Int Test Conf., pp. 480-487, 2003 https://doi.org/10.1109/TEST.2003.1270873
- S. Wang and S.K. Gupta, 'An automatic test pattern generator for minimizing switching activity during scan testing activity', IEEE Trans. Computer- Aided Design, vol. 21, Issue 8, pp. 954-968, Aug. 2002 https://doi.org/10.1109/TCAD.2002.800460
- A. Chandra and K. Chakrabarty, 'Test data compression for system-on-a-chip using Golomb codes', in Proc. IEEE VLSI Test Symp. pp. 113-120, April-May, 2000 https://doi.org/10.1109/VTEST.2000.843834
- S. Youhua, N. Togawa, M. Yanagisawa, T. Ohtsuki, and S. Kimura, 'Low Power Test Compression Technique for Designs with Multiple Scan Chain,' in Proc. Asian Test Symp., pp. 386-389, 2005 https://doi.org/10.1109/ATS.2005.76
- A Chandra and K Chakrabarty, 'Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression', in Proc. IEEE VLSI Test Symp. pp. 42-47, 2001 https://doi.org/10.1109/VTS.2001.923416
- A. Jas and N. A. Touba, 'Test vector decompression via cyclical scan chains and its application to testing core-based design', in Proc. Int Test Conf., pp. 458-464, Oct. 1998 https://doi.org/10.1109/TEST.1998.743186
- P.T. Gonciari, B.M. Al-Hashirni, and N. Nicolici, 'Variable-length input Huffman coding for system-on-a-chip test', IEEE Trans. Computer-Aided Design, vol. 22, Issue 6, pp. 783-796, June 2003 https://doi.org/10.1109/TCAD.2003.811451
- A. Jas, G.D. Jayabrata, M.E. Ng, and N. A. Touba, 'An Efficient Test Vector Compression Scheme Using Selective Huffman Coding', IEEE Trans. Computer-Aided Design, vol. 22, Issue 6, pp. 797-806, June 2003 https://doi.org/10.1109/TCAD.2003.811452
- K.J. Balakrishnan and N. A. Touba, 'Relating entropy theory to test data compression', in Proc. IEEE Euro. Test Symp., pp. 94-99, May 2004
- A. Chandra and K. Chakrabarty, 'A unified approach to reduce SOC test data volume, scan power and testing time,' IEEE Trans. Computer-Aided Design, vol. 22, pp. 352-363, Mar. 2003 https://doi.org/10.1109/TCAD.2002.807895
- M.H. Tehranipour, M. Nourani, K. Arabi, and A. Afzali-Kusha, 'Mixed RL-Huffman encoding for power reduction and data compression in scan test', in Proc. Int. Symp. Circuits and Systems, pp. 681-684, May 2004
- R. Sankaralingarn, P.R. Orugranti, and N. A. Touba, 'Static compaction techniques to control scan vector power dissipation', in Proc. VLSI Test Symp., pp. 35-40, April-May 2000 https://doi.org/10.1109/VTEST.2000.843824