JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression

  • Kim, Dooyoung (Dept. of Computer Science and Engineering, Hanyang University) ;
  • Ansari, M. Adil (Dept. of Computer Science and Engineering, Hanyang University) ;
  • Jung, Jihun (Dept. of Computer Science and Engineering, Hanyang University) ;
  • Park, Sungju (Dept. of Computer Science and Engineering, Hanyang University)
  • Received : 2015.12.11
  • Accepted : 2016.05.02
  • Published : 2016.10.30
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Abstract

Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.

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References

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