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http://dx.doi.org/10.5573/JSTS.2014.14.5.640

Reducing Test Power and Improving Test Effectiveness for Logic BIST  

Wang, Weizheng (College of computer and communication Engineering, Changsha University of Science and Technology)
Cai, Shuo (College of computer and communication Engineering, Changsha University of Science and Technology)
Xiang, Lingyun (College of computer and communication Engineering, Changsha University of Science and Technology)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.14, no.5, 2014 , pp. 640-648 More about this Journal
Abstract
Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.
Keywords
IC testing; BIST; test power; pseudorandom test data; fault coverage;
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1 K.M. Butler, J. Saxena, A. Jain, T. Fryars, J. Lewis and G. Hetherington, "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques," IEEE Proc. ITC, pp. 355-364, 2004.
2 Tobias Strauch, "Single Clock pulse Structure For Logic Test", IEEE transactions Very large Scale Integration (VLSI )system, 20(5):878-891, 2012.   DOI
3 J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, " A case study of IR-drop in structured at-speed testing," IEEE Proc. ITC, pp. 1098-1104, 2003.
4 M. ElShoukry, C. Ravikumar, and M. Tehranipoor, "Partial Gating Optimization for Power Reduction during Test Application," in Asian Test Symp., 2005, pp. 242-247.
5 Y. Yamato, X. Wen, M.A. Kochte, K. Miyase., S.Kajihara, Laung-Terng Wang. "A novel scan segmentation design method for avoiding shift timing failure in scan testing". In International Test Conference, pages 1-8, 2011.
6 J. T. Tudu, Erik Larsson, Virendra Singh, et al. "On Minimization of Peak Power for Scan Circuit during Test," In: Proc of European Test Symposium, 2009, 25-30
7 L. Lee, S. Narayan, M. Kapralos, et al. "Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation," In: Proc of the Design, Automation, and Test in Europe Conf., Mar. 2008, 1172-1177
8 X. Wen, K. Miyase, S. Kajihara, et al. "A Capture-Safe Test Generation Scheme for At-Speed Scan Testing," In: Proc of the European Test Symp., May 2008, 55-60
9 H. Furukawa, X. Wen, K. Miyase, et al. "CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing," In: Proc of the Asian Test Symp., Nov. 2008, 397-402
10 P. Girard, L. Guiller, C. Landrault, et al., "A Modified Clock Scheme for a Low Power BIST Pattern Generation," Proc. IEEE VLSI Test Symp., pp. 23-28, 2000.
11 J. Li, Q. Xu,Y. Hu, and X.W Li. "X-Filling for Simultaneous Shift-and Capture-Power Reduction in At-Speed Scan-Based Testing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2010, 18(7): 1081-1092   DOI
12 P.H. Bardell, W.H. McAnney, and J. Savir, "Built-In Test for VLSI: Pseudorandom Techniques," New York: Wiley, 1987.
13 T.-C. Huang and K.-J. Lee, "A token scan architecture for low power testing," in Proc. IEEE Int. Test Conf., Baltimore, MD, 2001, pp. 660-669.
14 S. Gerstendorfer and H.-J. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," IEEE Proc. ITC, pp. 77-84, 1999.
15 X. Lin and J. Rajski, "Test Power Reduction by Blocking Scan Cell Outputs," IEEE Proc. ATS, pp. 329-336, 2008.
16 M. E. Imhof, C. G. Zoellin, H.-J. Wunderlich, N. Maeding, and J. Leenstra, "Scan test planning for power reduction," in Proceedings of the 44th Design Automation Conference, 2007, pp.521-526
17 M. Elm, H. J. Wunderlich, M. E. Imhof, et al., "Scan chain clustering for test power reduction," ACM Proc. Design Automation Conference, pp. 828-833, 2008.
18 Y. Sato, S. Wang, T. Kato, K. Miyase and S. Kajihara, "Low Power BIST for Scan-Shift and Capture Power," IEEE Proc. Asian Test Symp., pp. 173-178, 2012.
19 S. Wang and S. K. Gupta, "LT-RTPG: A New Test-Per-Scan BIST TPG for Low Switching Activity," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 25, no. 8, pp. 1565-1574, 2006.   DOI   ScienceOn
20 M. Filipek, Y. Fukui, H. Iwata, G. Mrugalski, J. Rajiski, M. Takakura and J. Tyszer, "Low Power Decompressor and PRPG with Constant Value Broadcast," IEEE Proc. Asian Test Symp., pp. 84-89, 2011.
21 X. Lin and J. Rajski, "Adaptive Low Shift Power Test Pattern Generator for Logic BIST," Proc. IEEE Asian Test Symposium, pp. 355-360, 2010.
22 C. Zoellin, H. J. Wunderlich, N. Maeding, and J. Leenstraa, "BIST Power Reduction Using Scan-Chain Disable in the CELL Processor," in Proc. Int. Test Conf., Paper 32.3, 2006.
23 B. Ye, T.W Li, Q. Zhao, D. Zhou, X.H Wang and M. Luo, "A low power test pattern generation for bui lt-in self-test based circuits," International Journal of Electronics, Vol. 98, No. 3, 2011, 301-309.   DOI
24 S.C. Lei, F. Liang, Z. Y. Liu, X.Y. Wang, Z. Wang, "A Low Power Test Pattern Generator for BIST," IEICE Trans. Electron., Vol.E93-C, No.5, 2010, pp.696-702.   DOI
25 J. Tyszer, M. Filipek, G. Mrugalski, N. Mukherjee, J. Rajski, " New Test Compression Scheme Based on Low Power BIST," IEEE Proc. European Test Symposium, Paper 32.3, 2013.
26 D. Xiang, M. J. Chen, J. G. Sun, and H. Fujiwara, "Improving the effectiveness of scan-based BIST using scan chain partitioning," IEEE Trans. on Computer-Aided Design, vol. 24, no. 6, pp.916-927, 2005.   DOI   ScienceOn