• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.1
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• pp.52-59
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• 2009

In modern radars, dynamic range requirements far severed due to high CNR(Clutter-to-Noise Ratio) environment operation scenario. ADC spurious signal restricted the required dynamic range. In this paper, receiver gain of active phased array radar dependent on ADC nonlinear characteristic was analyzed. Within limited scope of ADC SFDR which blocks required system dynamic range, ADC dynamic range reaches trade-off with ADC SNR loss. Comparing antenna stage output noise voltage to that of ADC input, receiver gain was mathematically analyzed. Finally the whole contents were explained from the application example.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2131-2141
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• 2015

In this paper, we analyze ADC effect in IBFD system. Also, we design IBFD system with ADC effect, and evaluate BER performance of the system according to power of self-interference. Firstly, we describe a fundamentals of general IBFD system. And then we calculate and analyze characteristics of desired signal before and after ADC when residual self-interference is added to desired signal after RF cancellation. In this calculation, we have confirm some conditions for selection of # of ADC bit. Finally, we design IBFD system with ADC effect, and evaluate BER performance of the system by using Simulink simulation tool. As simulation results, we have confirmed that when power of residual self-interference is high before ADC, IBFD system must use high-bit ADC for decreasing quantization step. Also, we have confirmed that quantization step should be lower than one-third of amplitude of desired signal for effective communication with good performance.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.76-81
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• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Journal of Chest Surgery
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• v.37 no.12
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• pp.967-977
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• 2004

Background: DNA methylation is one of the important gene expression mechanisms of the cell. When cytosine of CpG dinucleotide in promotor is hypomethylated, expression of some genes that is controlled by this promoter is altered. In this study, the author investigated the effect of DNA demethylating agent, 5-aza-2'-deoxycytidine (ADC), on the expressions of cancer antigen genes, MHC and B7 in 4 lung cancer cell lines, NCIH1703, NCIH522, MRC-5, and A549. Material and Method: After treatment of cell lines, NCIH1703, NCIH522, MRC-5 and A549 with ADC (1 uM) for 48 hours, RT-PCR was performed by using the primers of MAGE, GAGE, NY-ESO-1, PSMA, CEA, and SCC antigen gene. In order to find the optimal ADC treatment condition for induction of cancer antigen, we studied the effect of ADC treatment time and dose on the cancer antigen gene expression. To know the effect of ADC on the expression of MHC or B7 and cell growth, cells were treated with 1 uM of ADC for 72 hours for FACS analysis or cells were treated with 0.2, 1 or 5 uM of ADC for 96 hours for cell counting. Result: After treatment of ADC (1 uM) for 48 hours, the expressions of MAGE, GAGE, NY-ESO-1, and PSMA genes increased in some cell lines. Among 6 MAGE isotypes tested, and gene expression of MAGE-1, -2, -3, -4 and -6 could be induced by ADC treatment. However, CEA gene expression did not change and SCC gene expression was decreased by ADC treatment. Gene expression was generally induced 24 - 28 hours after ADC treatment and expression of MAGE, GAGE, and NY-ESO-1 was maintained at least 14 days after ADC ADC teatment, and expression of MAGE, GAGE, and NY-ESO-1 was maintained at least 14 days after ADC teatment in ADC-Free medium. Most gene expression could be induced at 0.2 uM of ADC, but gene expression increased dependently on ADC treatment dose. The expression of MHC and B7 was not increased by ADC treatment in all four cell lines, and the growth rate of 4 cell lines decreased significantly with the increase of ADC concentrations. Conclusion: Treatment of lung cancer cell lines with ADC increases the gene expression MAGE, GAGE and NY-ESO-1 that are capable of induction of cytotoxic T lymphocyte response. We suggest that treatment with 1 uM of ADC for 48 hours and then culturing in ADC-free medium is optimal condition for induction of cancer antigen. However, ADC has no effect on MHC and B7 induction, additional modification for increase of expression of MHC, B7 and cytokine will be needed for production of efficient cancer cell vaccine.

• Journal of Semiconductor Engineering
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• v.2 no.1
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• pp.99-108
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• 2021

Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.83-92
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• 2004

In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.606-608
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• 2006

This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

• The Journal of the Korea institute of electronic communication sciences
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• v.6 no.4
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• pp.545-552
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• 2011

In this article, reference voltages in a general flash ADC are not obtained from a series of resistors but floating gates. When a behavior model simulation was performed in a pipelined ADC including the suggested flash ADC as a result of an ADC's overall function, it showed results that SNR is approximately 77 dB and resolution is 12 bit. And more than almost 90% showed INL within ${\pm}0.5$ LSB, and like INL, more than 90% showed DNL within ${\pm}0.5$ LSB.

• Journal of IKEEE
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• v.22 no.2
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• pp.514-517
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• 2018

In sensor systems, ADC (analog-to-digital converter) demands high resolution, low power consumption, and high signal bandwidth. Sigma-delta ADC achieves high resolution by high order structure and high over-sampling ratio, but it suffers from high power consumption and low signal bandwidth. SAR (successive-approximation-register) ADC achieves low power consumption, but there is a limitation to achieve high resolution due to process mismatch. This paper surveys architecture improvement of ADC to overcome these problems.