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A Novel Method for Time-Interleaved Subranging ADC 8bit 80MS/s in 0.18um CMOS  

Park, Ki-Chul (Division of Electronics and Information Engineering, Chonbuk University)
Kim, Kang-Jik (Division of Electronics and Information Engineering, Chonbuk University)
Cho, Seong-Ik (Division of Electronics and Information Engineering, Chonbuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.46, no.1, 2009 , pp. 76-81 More about this Journal
Abstract
A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.
Keywords
Sample and Hold Amplifier(SHA); Resister-String(RS); Control Switch(CS); Coarse flashADC(CADC); Fine flashADC(FADC);
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1 K.Y. Kim, N.Kusayanagi, and A. A. Abidi 'A 10-b, 100MS/s CMOS A/D converter,' IEEE J. Solid-State Circuits, vol.32, pp.302-311, Mar.1997   DOI   ScienceOn
2 K.El-Sankary, A.Assi, and M.Sawan, 'A new time-interleaved architecture for high-speed A/D converters.' IEEE. Nov. 2002
3 Byeong-Jin Kwon, Kang-Min Chung, ' Design of 8-bit CMOS Subranging ADC using Gate array', S.korea: 1992
4 B.P Brant and J.Lutsky, 'A 74mW 10-b, 20MSPS CMOS subranging ADC with 9.5 effective bits at nyquist,'IEEE J.Solid-State Circuits,vol34, pp.1788-1795, Dec. 1999   DOI   ScienceOn
5 Jung-Woong Moon, Hee-Suk Yang, and Seung-Hoon Lee, 'An 8b 200MHz Time- Interleaved Subranging ADC With a New Reference Voltage Switching Scheme', S.Korea: Sogang University, 2002