Browse > Article
http://dx.doi.org/10.5573/ieie.2016.53.7.017

A Mismatch-Insensitive 12b 60MS/s 0.18um CMOS Flash-SAR ADC  

Byun, Jae-Hyeok (Dept. of Electronic Engineering, Sogang University)
Kim, Won-Kang (Dept. of Electronic Engineering, Sogang University)
Park, Jun-Sang (Dept. of Electronic Engineering, Sogang University)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.53, no.7, 2016 , pp. 17-26 More about this Journal
Abstract
This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.
Keywords
Flash; SAR; ADC;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
연도 인용수 순위
1 Xiaoke Wen, et al., "A 12b 60MS/s SHA-Less Opamp-Sharing Pipeline A/D with Switch-Embedded Dual Input OTAs", in Proc. IEEE ISCAS, May 2012, pp. 802-805.
2 Chun C. Lee, Michael P. Flynn, "A SAR-Assisted Two-Stage Pipeline ADC," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859-869, April 2011.   DOI
3 K. H. Lee, et al., "A 12b 50 MS/s 21.6 mW 0.18 ${\mu}$m CMOS ADC maximally sharing capacitors and op-amps," IEEE Trans. Circuits Syst. I, vol. 58, no. 9, pp. 2127-2136, Sept. 2011.   DOI
4 C. C. Lee and M. P. Flynn, "A 12b 50MS/s 3.5mW SAR Assisted 2-stage Pipeline ADC," in Symp. VLSI Circuits Dig. Tech. Papers, June 2010, pp. 239-240.
5 M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, "A 10b 50MS/s 820uW SAR ADC with on-chip digital calibration," in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 384-385.
6 Y. Chen, S. Tsukamoto, and T. Kuroda, "A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS," in Proc. ASSCC, Nov. 2009, pp. 145-148.
7 C. C. Liu, et al., "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.   DOI
8 Y. Zhu, et al., "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS," IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.   DOI
9 M. Furuta, M. Nozawa, and T. Itakura, "A $0.06mm^2$ 8.9b ENOB 40MS/s Pipelined SAR ADC in 65nm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 382-383.
10 U. F. Chio, et al., "Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 8, pp. 607-611, Aug. 2010.   DOI
11 Y. Z. Lin, et al., "A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 3, pp. 570-581, Mar. 2013.   DOI
12 H. L. Park, et al., "A 6b 1.2 GS/s 47.8 mW $0.17mm^2$ 65 nm CMOS ADC for High-Rate WPAN Systems," Journal of Semiconductor Technology and Science, vol. 11, no. 2, pp. 95-103, June 2011.   DOI
13 Y. K. Cho, J, H, Jung, and K. C. Lee, et al., "A 9-bit 100-MS/s Flash-SAR ADC without Track-and-Hold Circuits," in Symp. ISWCS, Aug. 2012, pp. 880-884.
14 B. G. Lee and R. Tsang, "A 10-bit 50 MS/s pipeline ADC with capacitor-sharing and variable-gm opamp," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 883-890, Mar. 2009.   DOI
15 K. J. Lee, K. J. Moon, K. S. Ma, K. H. Moon, and J. W. Kim, "A 65nm CMOS 1.2V 12b 30MS/s ADC with capacitive reference scaling," in Proc. IEEE CICC, Sept. 2008, pp. 165-168.
16 M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS," J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec. 2001.   DOI
17 K. Uyttenhove and M. S. J. Steyaert, "A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-um CMOS," J. Solid-State Circuits, vol. 38, no. 7, pp. 1115-1122, July. 2003.   DOI
18 J. Y. Um, et al., "A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits," IEEE Trans. Circuits Syst. I , Fundam. Theory Appl., vol. 60, no. 11, pp. 2845-2856, Nov. 2013.   DOI
19 Y. S. Cho, et al., "A Non-Calibrated 2x Interleaved 10b 120MS/s Pipeline SAR ADC with Minimized Channel Offset Mismatch," Journal of The Institute of Electronics and Information Engineer, Vol.52, SD, NO.9, pp. 63-73, Sept. 2015.
20 Y. M. Kim, J. S. Park, Y. J. Shin, and S. H. Lee, "An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors," Analog Integrated Circuits and Signal Processing, vol. 80, no. 1, pp. 49-57, July 2014.   DOI
21 J. H. Byun, et al., "A 12b 60MS/s 0.11um Flash-SAR ADC Using a Mismatch-Free Shared Sampling Network," in Proc. IEEE Int. SoC Design Conf, Nov. 2015, pp. 79-80.
22 H. Alzaher and M. Ismail, "A CMOS fully balanced differential difference amplifier and its application," IEEE Transactions on Circuit and Systems II, vol. 48, no. 6, pp. 614-620, June 2001.   DOI
23 C. Lane, "A 10-bit 60MSPS Flash ADC," Proc. BCTM, pp. 44-47, Sept. 1989.
24 Y. J. Kim, H. C. Choi, S. W. Yoo, S. H. Lee, "A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC," in Proc. IEEE CICC, Sept. 2007, pp. 185-188.
25 C. C. Lee, et al., "A 12b 70MS/s SAR ADC with digital startup calibration in 14nm CMOS," in Symp. VLSI Circuits Dig. Tech. Papers, June 2015, pp. C62-C63.
26 W. Liu, et al., "A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration," in Proc. IEEE CICC, Sept, 2012, pp. 1-4.