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A 6-bit, 70MHz Modified Interpolation-2 Flash ADC with an Error Correction Circuit  

박정주 (충북대학교 정보통신공학과)
조경록 (충북대학교 정보통신공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.3, 2004 , pp. 83-92 More about this Journal
Abstract
In this thesis, a modified interpolation-2 6-bit 70MHz ADC is proposed minimizing chip area and power consumption, which includes an error correction circuit. The conventional flash ADC without interpolation comparators suffers from large chip area and more power consumption due to 2n resistors and 2n-1 comparators. Although the flash ADC with interpolation-4 comparators has small area, SNR, INL and DNL are degraded by comparison with the interpolation -2 comparator. We fabricated the proposed 6-bit ADC with interpolation-2 comparators using 0.18${\mu}{\textrm}{m}$ CMOS process. The ADC is composed of 32-resistors, 31 comparators, amplifiers, latches, error correction circuit, thermometer code detector and encoder As the results, power consumption is reduced to 40mW at 3.3V which is saving about 50% than a flash ADC without interpolation comparators, and area is reduced by 20%. SNR is increased by 75% in comparison with that of a flash ADC with interpolation-4 comparators.
Keywords
flash ADC; interpolation; error correction;
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