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http://dx.doi.org/10.22895/jse.2020.0105

Brief Overview on Design Techniques and Architectures of SAR ADCs  

Park, Kunwoo (School of Electrical Engineering, KAIST)
Chang, Dong-Jin (School of Electrical Engineering, KAIST)
Ryu, Seung-Tak (School of Electrical Engineering, KAIST)
Publication Information
Journal of Semiconductor Engineering / v.2, no.1, 2021 , pp. 99-108 More about this Journal
Abstract
Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) seem to become the hottest ADC architecture during the past decade in implementing energy-efficient high performance ADCs. In this overview, we will review what kind of circuit techniques and architectural advances have contributed to place the SAR ADC architecture at its current position, beginning from a single SAR ADC and moving to various hybrid architectures. At the end of this overview, a recently reported compact and high-speed SAR-Flash ADC is introduced as one design example of SAR-based hybrid ADC architecture.
Keywords
SAR ADC; asynchronous SAR ADC; loop-unrolled SAR ADC; decision redundancy; digital error correction; multi-bit/cycle SAR ADC; hybrid SAR ADC; pipelined-SAR; sub-ranging SAR; flash-SAR; noise-shaping SAR;
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