• 대한전자공학회논문지SD
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• 제41권2호
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• pp.9-15
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• 2004

본 논문에서는 부분공핍(partially-depleted : PD) 영역과 완전공핍(fully-depleted : FD) 영역을 나누는 임계 전면 게이트 전압 V/sub c/의 해석적 표현을 이용해서 PD 영역과 FD 영역의 천이를 정확히 설명하는 해석적 표면전위 모델(analytical surface potential model)을 소개한다. 이 모델은 모든 동작영역(subthreshold에서 strong inversion까지)에서 유효하고 반복 계산 절차 (iteration procedure)인 수치 해석적 방법보다 훨씬 짧은 계산시간이 걸린다. 이 모델에 기초한 charge sheet 모델이 모는 동작영역에 유효한 드레인 전류의 단일 공식을 유도하는데 사용된다. 대부분의 secondary 효과들이 charge sheet 모델에 쉽게 포함되고 그 모델의 결과들은 수치해석 결과와 실험 결과를 비교적 정확히 일치한다. 세 가지의 smoothing 함수가 사용될지 라도 표면전위 미분 값은 연속이다 더욱 중요한 점은 smoothing 함수에 사용된 파라미터들은 공정 파라미터들에 크게 의존하지 않는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.187-194
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• 2005

An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-to-source voltage at various temperatures and exponent $C(i.e\;1/f^c$ is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to $0.1{\mu}m$ technology is considered. It is analyzed that l/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.

• 한국정보통신학회논문지
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• 제11권10호
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• pp.1910-1915
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• 2007

본 논문에서는 NQS(non-quasi-static)효과를 고려한 FD(fully depleted)-SOI(silicon-on-insulator) MOSFETs의 고주파 소신호 모델링을 위한 등가회로 변수들을 간단하고 정확히 추출하는 방법을 제시하였다. 제시된 추출방법은 임피던스와 어드미턴스 행렬계산으로 S-파라미터의 측정 결과로부터 MOSFET의 외부 기생용량과 기생저항을 제거하여 물리적인 특성을 바탕으로 한 MOSFET의 내부등가회로변수가 간단히 추출되어진다. 제시된 방법으로 등가 회로를 구한 후 Y-파라미터를 계산하여 측정치와 비교한 결과 500MHz부터 200Hz까지 잘 일치함을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.111-120
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• 2011

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

• 반도체디스플레이기술학회지
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• 제3권4호
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.95-96
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• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.262-271
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• 2011

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• 한국전기전자재료학회논문지
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• 제25권2호
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• pp.96-99
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• 2012

We fabricated fully depleted (FD) SOI-based 1T-DRAM cells with planar channel or recessed channel and the electrical characteristics were investigated. In particular, the dependence of memory operating mode on the channel structure of 1T-DRAM cells was evaluated. As a result, the gate induced drain leakage current (GIDL) mode showed a better memory property for planar type 1T-DRAM. On the other hand, the impact ionization (II) mode is more effective for recessed type.