• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.7
• /
• pp.1-7
• /
• 2010

The device performances of accumulation-mode Pi-gate pMOSFETs with different fin widths have been characterized at high operating temperatures. The device fin height is 10nm and fin widths are 30nm, 40nm, and 50nm. The variation of the drain current, threshold voltage, subthreshold swing, effective mobility, and leakage current have been investigated as a function of operating temperatures. The drain current at high temperature is slightly larger than at room temperature. The variation of the threshold voltage as a function of the operating temperature is smaller than that of the inversion-mode MOSFETs. The effective mobility is decreased with the increase of operating temperature. It is observed that the effective mobility is enhanced as the fin width decreases.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.554-562
• /
• 2015

This paper presents the design and analysis of gate-recessed AlGaN/GaN Fin-type Field-Effect Transistor (FinFET). The three-dimensional (3-D) technology computer-aided design (TCAD) simulations were performed to analyze the direct-current (DC) and radio-frequency (RF) characteristics for AlGaN/GaN FinFETs. The fin width ($W_{fin}$) and the height of GaN layer ($H_{GaN}$) are the design parameters used to improve the electrical performances of gate-recessed AlGaN/GaN FinFET.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.1
• /
• pp.16-21
• /
• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.4
• /
• pp.302-310
• /
• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.749-752
• /
• 2014

The device performance of n-channel MuGFET with different fin width, existence of spacer and channel length has been characterized. Tri-Gate structure(fin number=10) has been used. There are four kinds of Tri-Gate with fin width=55nm with spacer, fin width=70nm with spacer, fin width=55nm without spacer, fin width=70nm without spacer. DIBL, subthreshold swing, Vt roll-off, (above Short Channel Effect)and hot carrier stress degradation have been measured. From the experiment results, short Channel Effect with spacer was decreased, hot carrier degradation with spacer and narrow fin width was decreased. Therefore, layout of LDD structure with spacer and narrow fin width is desirable in short channel effect and hot carrier degradation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2009.10a
• /
• pp.907-909
• /
• 2009

In this paper, the dependence of threshold voltage on the gate oxide thickness, which it mostly influenced on short channel effects in fabrication of FinFET, has been investigated. The transport model based on three dimensional Possion's equation has been used to analyze influence on gate oxide thickness. The gate oxide thickness is the most important factor to influence on the threshold voltage in nano structure FinFET. The potential distributions of this model are compared with those of three dimensional numerical simulation to verify this model. As a result, since potential model presented in this paper is good agreement with hree dimensional numerical model, the threshold voltage characteristics have been considered according to the gate oxide thickness of FinFET.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.4
• /
• pp.35-42
• /
• 2013

In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.

• Journal of information and communication convergence engineering
• /
• v.7 no.1
• /
• pp.57-61
• /
• 2009

This paper has presented the subthreshold current model of FinFET using the potential variation in the doped channel based on the analytical solution of three dimensional Poisson's equation. The model has been verified by the comparison with the data from 3D numerical device simulator. The variation of subthreshold current with front and back gate bias has been studied. The variation of subthreshold swing and threshold voltage with front and back gate bias has been investigated.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.9
• /
• pp.1599-1604
• /
• 2008

In this paper, it has been analyzed how transport characteristics is influenced on gate oxide properties in the subthreshold region as nano structure FinFET is fabricated. The analytical model is used to derive transport model, and Possion equation is used to obtain analytical model. The thermionic emission and tunneling current to have an influence on subthreshold current conduction are analyzed for nano-structure FinFET, and subthreshold swings of this paper are compared with those of two dimensional simulation to verify this model. As a result, transport model presented in this paper is good agreement with two dimensional simulation model, and this study shows that the transport characteristics have been changed by gate oxide properties. As gate length becomes smaller, funneling characteristics, one of the most important transport mechanism, have been analyzed.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.3
• /
• pp.156-161
• /
• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.