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http://dx.doi.org/10.5573/ieek.2013.50.4.035

Analysis of Process and Layout Dependent Analog Performance of FinFET Structures using 3D Device Simulator  

Noh, SeokSoon (College of Information and Communication Engineering, Sungkyunkwan University)
Kwon, KeeWon (College of Information and Communication Engineering, Sungkyunkwan University)
Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.50, no.4, 2013 , pp. 35-42 More about this Journal
Abstract
In this paper, the analog performance of FinFET structure was estimated by extracting the DC/AC characteristics of the 22 nm process FinFET structures with different layout considering spacer and SEG using 3D device simulator, Sentaurus. Based on the analysis results, layout methods to enhance the analog performance of multi-fin FinFET structures are proposed. By adding the spacer and SEG structures, the drive current of 1-fin FinFET increases. However, the unity gain frequency, $f_T$, reduces by 19.4 % due to the increase in the total capacitance caused by the added spacer. If the process element is not included in multi-fin FinFET, replacing 1-finger with 2-finger structure brings approximately 10 % of analog performance improvement. Considering the process factors, we propose methods to maximize the analog performance by optimizing the interconnect and gate structures.
Keywords
FinFET; finger; 3-stage ring oscillator; unity gain frequency;
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