• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.1C
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• pp.40-44
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• 2010

The timing error detector(TED) employed in the closed loop type timing synchronization scheme for an MQASK all digital receiver suffers from the selfnoise-induced timing jitter. To eliminate the timing jitter a prefilter can be added in front of the TED. The prefilter method, however, degrades the stability and timing acquisition performance due to the loop delay and increases the complexity of the synchronizer. This paper proposes a polyphase filter type resampler approach to optimize the performance and architecture of the synchronizer simultaneously. The proposed scheme uses two resamplers which performs matched filtering and matched prefiltering so that the loop delay is minimized with minimal hardware resources. Simulation results showed an excellent acquisition performance with reduced timing jitter.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.133-138
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The signal through a small RC time constant circuit has almost same loop filter output voltage. The signal through a large RC time constant circuit has the average value of loop filter output voltage and does as a role of reference voltage to the comparator. The output of the comparator controls the sub-charge pump which provide a current to LPF. When the loop filter output voltage increases, the sub-charge pump discharges the loop filter and decreases loop filter output voltage. When the loop filter output voltage decreases, the sub-charge pump charges the loop filter and increases loop filter output voltage. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• Broadcasting and Media Magazine
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• v.24 no.4
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• pp.87-101
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• 2019

JVET(Joint Video Experts Team)에서 새로운 비디오 압축 표준으로 진행 중인 VVC(Versatile Video Coding)에서는 HEVC(High Efficiency Video Coding)의 기술을 근간으로 부호화 효율을 높일 수 있는 다양한 새로운 기술들을 채택하고 있다. 인루프 필터(In-Loop Filter)는 복원영상의 화질을 향상시키기 위한 기술로 주관적 화질 개선뿐만 아니라 부호화 효율을 향상시키는 기술로 기존 HEVC의 확장 기술 및 새로운 인루프 필터 기술을 채택하고 있다. 본 고에서는 VVC의 CD에 채택되어 있는 인루프 필터 기술들을 소개한다. 인루프 필터 기술은 HEVC에 채택되어 있는 디블록킹 필터(Deblocking Filter: DF)와 SAO(Sample Adaptive Offset), 새로이 추가된 ALF(Adaptive Loop Filter)의 3가지의 필터와 LMCS(Luma Mapping with Chroma Scaling) 기술을 포함하고 있다. 이들 인루프 필터 기술은 주관적 화질 개선과 부호화 효율을 크게 개선하고 있으며, 2020년 7월 FDIS(Final Draft International Standard) 완료를 앞두고 인루프 필터링의 다양화로 인한 성능과 복잡도를 고려한 간소화 및 병렬처리 등의 고속화에 대한 표준화가 지속적으로 이루어질 전망이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2387-2394
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• 2013

A low spur phase-locked loop (PLL) with FVCO-sampled feedforward loop-filter has been proposed. Conventional PLL has loop filter made of a resistor and capacitors. The proposed PLL is working stably with the filter consisted of capacitors and a switch. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2326-2332
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.11
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• pp.2009-2014
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• 2017

A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.7
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• pp.999-1008
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• 1993

동기추적 루프는 수신된 확산 부호의 동적 파형에 대한 추적을 수행함에 있어 AWGN 존재 하에서 낮은 동기추적 지터를 목적으로 설계되며, 전송지연에 대한 효율적인 추적을 위한 루프의 대역폭이 요구된다. 본 논문에서는 지연동기루프의 최적 설계를 위한 대역통과필터의 대역폭에 대하여 고찰하였다. NRZ 데이타의 경우 단극, 쌍극 및 이상적 Butterworth 대역통과 필터를 채용한 비코히어런트 BLL의 재곱손실을 구하였으며, 이를 통해 루프의 동기추적 지터를 최소화하는 대역통과필터의 최적의 대역폭을 주어진 데이타율과 수신비트에너지대 잡음밀도비에 대해 구하였다. 결과로서 NRZ 데이타의 경우 합리적인 대역통과필터의 최적대역폭이 존재함을 알 수 있으며, 아울러 DLL의 동기추적 지터에 대한 성능은 사용된 필터의 종류에 대해서는 비교적 민감하지 않음을 알 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.8
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• pp.1068-1075
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• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.