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http://dx.doi.org/10.17661/jkiiect.2022.15.2.89

A Discrete-Time Loop Filter Phase-locked loop with a Frequency Fluctuation Converting Circuit  

Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University)
Park, Kyung-Seok (Department of Electronic Engineering, Pukyong National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.15, no.2, 2022 , pp. 89-94 More about this Journal
Abstract
In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.
Keywords
Discrete loop filter; Negative feedback; Jitter Characteristic;
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