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http://dx.doi.org/10.17661/jkiiect.2021.14.1.37

A low noise PLL with frequency voltage converter and loop filter voltage detector  

Choi, Hyek-Hwan (Department of Electronic Engineering, Pukyong National University)
Publication Information
The Journal of Korea Institute of Information, Electronics, and Communication Technology / v.14, no.1, 2021 , pp. 37-42 More about this Journal
Abstract
This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.
Keywords
PLL; Loop Filter; Voltage Detector; Frequency Voltage Converter; Charge Pump;
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