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http://dx.doi.org/10.6109/jkiice.2016.20.12.2326

A PLL with high-speed operating discrete loop filter  

An, Seong-Jin (Department of Electronic Engineering, Pukyong National University)
Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.20, no.12, 2016 , pp. 2326-2332 More about this Journal
Abstract
In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.
Keywords
PLL; discrete loop filter; switch;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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1 M. K. Hati and K. B. Tarun, "A PFD and charge pump switching circuit to optimize the output phase noise of the PLL in 0.13-um CMOS," IEEE 2015 International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Bangalore, pp. 1-6, Jan. 2015.
2 K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez, and S. H. K. Embabi, "A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 866-874, June 2003.   DOI
3 S. R. Han, C.N. Chuang and S. I. Liu, "A time-constant calibrated phase-locked loop with a fast-locked time," IEEE Transactions on Circuits and Systems, vol. 54, no.1, pp. 34-37, Jan. 2007.   DOI
4 H. S. Jang, and Y. S. Choi, "An available capacitance increasing PLL with two voltage controlled oscillator gains," IEEK SD, vol. 51, no. 7, pp. 82-88, July 2014.
5 Y. G. Song, Y. S. Choi, and J.G. Ryu, "A phase locked loop with resistance and capacitance scaling scheme," IEEK SD, vol. 46, no. 4, pp. 37-44, April 2009.
6 H. C. Luong and G.C.T. Leung, Low-Voltage CMOS RF frequency synthesizers. Cambridge. 2004.
7 K. J. Wang, A. Swaminathan, I. Galton, "Spurious-tone suppression techniques applied to a wide-bandwidth 2.4GHz fractional-N PLL" IEEE J. Solid-State Circuit, pp. 342-618, Feb. 2008.
8 J. Craninckx, and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthesizer," IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC, pp. 372-373, Feb. 1998.
9 K. J. Wang, I. Galton "A discrete-time model for the design of type-II PLLs with passive sampled loop filters" IEEE Transactions on Circuits and Systems, vol. 58, no. 2, pp. 264-275, Feb. 2011.   DOI