• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.26-31
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• 2009

A new LFSR based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, smax, virtually. The performance of a conventional LFSR reseeding scheme highly depends on smax. In this paper, by using different clock frequencies between an LFSR and scan chains, and grouping the scan cells, we could reduce smax virtually. H the clock frequency which is slower than the clock frequency for the scan chain by n times is used for LFSR, successive n scan cells are filled with the same data; such that the number of specified bits can be reduced with an efficient grouping of scan cells. Since the efficiency of the proposed scheme depends on the grouping mechanism, a new graph-based scan cell grouping heuristic has been proposed. The simulation results on the largest ISCAS 89 benchmark circuit show that the proposed scheme requires less memory storage with significantly smaller area overhead compared to the previous test compression schemes.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.43-48
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• 2008

Power consumption during test can be much higher than that during normal operation since test vectors are determined independently. In order to reduce the power consumption during test process, a new BIST(Built-In Self Test) architecture is proposed. In the proposed architecture, test vectors generated by an LFSR(Linear Feedback Shift Resister) are transformed into the new patterns with low transitions using Bit Generator and Bit Dropper. Experiments performed on ISCAS'89 benchmark circuits show that transition reduction during scan testing can be achieved by 62% without loss of fault coverage. Therefore the new architecture is a viable solution for reducing both peak and average power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1A
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• pp.66-72
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• 2002

In this paper, we implemented the GenJTAG, a CAD tool, which generates a code of boundary scan circuit supporing a board level testing and d BIST(Built-In Self Test) written in verilog-HDL. A boundary scan circuit code that supports user's own BIST instructions is generated based on the informations from the users. Most CAD tools hardly allow users to add their own BIST instructions because the generated code described in gate-level. But the GenJTAG generates a behavioral boundary scan circuit code so users can easily make a change on the generated code.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.11 s.254
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• pp.1335-1347
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• 2006

Surface energies calculated from measured contact angles between several solutions and test samples, such as Si wafer, $Al_2O_3$, $SiO_2$, PTFE(Polytertrafluoroethylene), and DLC(Diamond Like Carbon) films, based on geometric mean method and Lewis acid base method. In order to relate roughness to adhesion force, surface roughness of test samples were scanned large area and small by AFM(Atomic Force Microscopy). Roughness was representative of test samples in large scan area and comparable with AFM tip radius in small scan area. Adhesion forces between AFM tip and test samples were matched well with order of roughness rather then surface energy. When AFM tips having different radius were used to measure adhesion force on DLCI film, sharper AFM tip was, smaller adhesion force was measured. Therefore contact area was more important factor to determine adhesion force.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.9
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• pp.1177-1184
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• 1999

본 논문에서는 스캔플립프롭 선택 시간이 짧고 높은 고장 검출률(fault coverage)을 얻을 수 있는 새로운 부분스캔 설계 기술을 제안한다. 순차회로에서 테스트패턴 생성을 용이하게 하기 위하여 완전스캔 및 부분스캔 설계 기술이 널리 이용되고 있다. 스캔 설계로 인한 추가영역을 최소화 하고 최대의 고장 검출률을 목표로 하는 부분스캔 기술은 크게 구조분석과 테스트 가능도(testability)에 의한 설계 기술로 나누어 볼 수 있다. 구조분석에 의한 부분스캔은 짧은 시간에 스캔플립프롭을 선택할 수 있지만 고장 검출률은 낮다. 반면 테스트 가능도에 의한 부분스캔은 구조분석에 의한 부분스캔보다 스캔플립프롭의 선택 시간이 많이 걸리는 단점이 있지만 높은 고장 검출률을 나타낸다. 본 논문에서는 구조분석에 의한 부분스캔과 테스트 가능도에 의한 부분스캔 설계 기술의 장단점을 비교.분석하여 통합함으로써 스캔플립프롭 선택 시간을 단축하고 고장 검출률을 높일 수 있는 새로운 부분스캔 설계 기술을 제안한다. 실험결과 대부분의 ISCAS89 벤치마크 회로에서 스캔플립프롭 선택 시간은 현격히 감소하였고 비교적 높은 고장 검출률을 나타내었다.Abstract This paper provides a new partial scan design technique which not only reduces the time for selecting scan flip-flops but also improves fault coverage. To simplify the problem of the test pattern generation in the sequential circuits, full scan and partial scan design techniques have been widely adopted. The partial scan techniques which aim at minimizing the area overhead while maximizing the fault coverage, can be classified into the techniques based on structural analysis and testabilities. In case of the partial scan by structural analysis, it does not take much time to select scan flip-flops, but fault coverage is low. On the other hand, although the partial scan by testabilities generally results in high fault coverage, it requires more time to select scan flip-flops than the former method. In this paper, we analyzed and unified the strengths of the techniques by structural analysis and by testabilities. The new partial scan design technique not only reduces the time for selecting scan flip-flops but also improves fault coverage. Test results demonstrate the remarkable reduction of the time to select the scan flip-flops and high fault coverage in most ISCAS89 benchmark circuits.

• Korean Journal of Construction Engineering and Management
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• v.25 no.2
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• pp.69-80
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• 2024

Currently rebar spacing inspection is carried out by human inspectors who heavily rely on their individual experience, lacking a guarantee of objectivity and accuracy in the inspection process. In addition, if incorrectly placed rebars are identified, the inspector need to correct them. Recently, laser scanning and AR technologies have been widely used because of their merits of measurement accuracy and visualization. This study proposes a technology for rebar spacing inspection and fixing by combining laser scanning and AR technology. First, scan data acquisition of rebar layers is performed and the raw scan data is processed. Second, AR-based visualization and fixing are performed by comparing the design model with the model generated from the scan data. To verify the developed technique, performance comparison test is conducted by comparing with existing drawing-based method in terms of inspection time, error detection rate, cognitive load, and situational awareness ability. It is found from the result of the experiment that the AR-based rebar inspection and fixing technology is faster than the drawing-based method, but there was no significant difference between the two groups in error identification rate, cognitive load, and situational awareness ability. Based on the experimental results, the proposed AR-based rebar spacing inspection and fixing technology is expected to be highly useful throughout the construction industry.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.61-71
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• 2003

Interconnect test for highly integrated environments like SoC, becomes more important as the complexity of a circuit increases. This importance is from two facts, test time and complete diagnosis. Since the interconnect test between IPs is based on the scan technology such as IEEE1149.1 and IEEE P1500, it takes long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue because a defect on interconnects are shown as a defect on a chip. But generally, interconnect test algorithms that need the short test time can not do complete diagnosis and algorithms that perform complete diagnosis need long test time. A new interconnect test algorithm is developed. The new algorithm can provide a complete diagnosis for all faults with shorter test length compared to the previous algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.83-90
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• 2004

This paper proposes an efficient scan testing method for compression of test input data and reduction of test power for SOC. The proposed method determines whether some parts of a test response can be reused as a part of next input test data on the analysis of deterministic test data and its response. Our experimental results show that benchmark circuits have a high similarity between un-compacted deterministic input test data and its response. The proposed testing method achieves the average of 29.4% reduction of power dissipation based on the number of test clock and 69.7% reduction of test data for ISCAS'89 benchmark circuits.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.99-107
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• 2003

This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.