Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low Cost SOC(System-On-a-Chip) Testing Method for Reduction of Test Data and Power Dissipation

테스트 데이터와 전력소비 단축을 위한 저비용 SOC 테스트 기법

  • Hur Yongmin (Department of Computer System Engineering, Dong Seoul College) ;
  • Lin Chi-ho (Department of Computer Science, Semyung University)
  • 허용민 (동서울대학 컴퓨터시스템과) ;
  • 인치호 (세명대학교 컴퓨터학과)
  • Published : 2004.12.01
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Abstract

This paper proposes an efficient scan testing method for compression of test input data and reduction of test power for SOC. The proposed method determines whether some parts of a test response can be reused as a part of next input test data on the analysis of deterministic test data and its response. Our experimental results show that benchmark circuits have a high similarity between un-compacted deterministic input test data and its response. The proposed testing method achieves the average of 29.4% reduction of power dissipation based on the number of test clock and 69.7% reduction of test data for ISCAS'89 benchmark circuits.

본 논문은 SOC의 테스트 데이터 압축과 전력소비를 단축시키기 위한 효율적인 스캔 테스트 방법을 제안한다. 제안된 테스트 방법은 deterministic 테스트 데이터와 그 출력응답을 분석하여 출력응답의 일부분이 차기에 입력될 테스트 데이터로 재사용될 수 있는지를 결정한다. 실험결과, 비압축된 deterministic 입력 테스트 데이터와 그 응답간에 높은 유사도가 있음을 알 수 있다. 제안된 테스트 방법은 ISCAS'89 벤치마크 회로를 대상으로 소요되는 클럭 시간을 기준으로 평균 29.4%의 전력소비단축과 69.7%의 테스트 데이터 압축을 가져온다.

Keywords

References

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