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A Non-Scan Design-For-Test Technique for RTL Controllers/Datapaths based on Testability Analysis  

Kim, Sung-Il (숭실대학교 컴퓨터학부)
Yang, Sun-Woong (숭실대학교 컴퓨터학부)
Kim, Moon-Joon (숭실대학교 컴퓨터학부)
Park, Jae-Heung (숭실대학교 컴퓨터학부)
Kim, Seok-Yoon (숭실대학교 컴퓨터학부)
Chang, Hoon (숭실대학교 컴퓨터학부)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.30, no.2, 2003 , pp. 99-107 More about this Journal
Abstract
This paper proposes a design for testability (DFT) and testability analysis method for register-transfer level (RTL) circuits. The proposed method executes testability analysis - controllability and observability - on the RTL circuit and determines the insertion points to enhance the testability. Then with the associated priority based on the testability, we insert only a few of the test multiplexers resulting in minimized area overhead. Experimental results shows a higher fault coverage and a shorter test generation time than the scan method. Also, the proposed method takes a shorter test application time required.
Keywords
RTL; DFT; Testability; Testability;
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